A Three Phase Interleaved Boost Converter with L & C Voltage Extension Mechanism

In this paper a high step-up dc-dc voltage converter is proposed. The proposed converter employs coupled inductors and voltage extension capacitors for obtaining a high voltage gain. The coupled inductors and extension capacitors are merged in traditional interleaved boost converters to get the additional advantage of high step-up voltage conversion ratio and reduced voltage stress on switches along with existing features of interleaved boost converters. The main operating principle of the proposed converter is discussed and the key principle waveforms and equations are analysed. A simulation in PSIM is carried out for the proposed converter as well as traditional interleaved boost converter for the same parameters which shows that the proposed converter has better performance as compared to the traditional interleaved boost converter. Finally, an experiment is carried on a 32 W, 20 V input, 160 V output prototype in the laboratory for experimental validation of the proposed converter. Important future directions have also been given for future research on the proposed topology.


INTRODUCTION
Renewable energy sources are becoming more and more popular due to low maintenance and less pollution.Most of the renewable energy sources generate power at low dc voltages and therefore a high step-up dc-dc voltage conversion is needed as in case of photovoltaic and fuel cells.The traditional boost converter does not meet this requirement as it must operate at very low duty cycle and there is a very high voltage stress across its semiconductor switches.During the last two decades increased research has been carried out on power electronics converters and especially a lot of research has been done on high step-up dc-dc converter topologies [1][2][3][4].
A cascaded/two stage boost converter which uses two boost converters in series is used to achieve high step-up voltage gain.However, the overall efficiency is the product of the efficiencies of two converters and is low [5,6].Quadratic boost converters which simplify the cascaded boost into a single switch structure are used to achieve the high step-up voltage conversion ratio.The voltage gain is equal to the product of the gains of two boost converters [7,8].A three level boost converter is presented in [9,10].Three level boost converter offers the advantage of reducing the voltage stresses across the semiconductor switches, but does not improve the voltage gain.
High step-up converters with voltage multiplier cells are presented in [11][12][13].This method uses voltage multiplier cells to achieve high step-up voltage conversion ratio.Each cell is made of two capacitors and two diodes.However, for high voltage gain several numbers of cells are required.Coupling the inductors among the phases of interleaved boost converters reduces the current ripples and also helps in obtaining high stepup voltage conversion ratio.However, the existence of leakage inductance can cause large voltage overshoots [14].Switched capacitor step-up converters can also achieve high voltage gain, however the efficiency of switched capacitor circuits is very low [15].
To get a high step-up voltage conversion ratio a new topology of dc-dc converter is presented in this paper.The idea is obtained by using coupled inductors and voltage extension capacitors in the traditional interleaved boost converter.This helps in additional advantages of high voltage gain and reduced voltage stress of switches along with existing features of interleaved topologies.Fig. 1(b) shows the circuit diagram of the proposed converter.It is a three phase interleaved boost converter with coupled inductors in the first phase and an extension capacitor in each second and third phase.In the proposed technique coupled inductors with turn ratio of x are always used in the first phase and extension capacitors are used in the rest of phases.The number of extension capacitors is (m−1), where m is the number of phases.The idea can be implemented for more than three phases.Increasing x and m will increase the voltage conversion ratio to a higher degree.Fig. 1(a) and 1(c) shows the two phases and m phase versions of the proposed converter respectively.The three phase version of the proposed converter shown in Fig. 1(b) is further analysed in this paper.This paper is an extension of our previous work presented in the conference mentioned in Ref [17].

Principle of Operation of the Proposed Converter
The circuit diagram of the proposed converter is shown in Fig. 1(b) which is a three phase interleaved boost converter with coupled inductors and two voltage extension capacitors.S 1 , S 2 and S 3 are the active switch of phase#1, Phase#2 and phase#3 respectively.D 1 , D 2 and D 3 are the rectifying diodes of three phases.L 1 is filter inductor of phase#1 and L 2 is filter inductor of phase#2.L C is the coupled inductor in phase#3 with primary winding inductor L P and secondary winding inductor L S .C 1 and C 2 are the extension capacitors connected in phase#1 and phase#2 respectively.C O is the output filtering capacitor and R O is load resistance.
For the proposed converter, the following assumptions are made.The turn ratio n of the two coupled inductors L P and L S is defined as follows [16]: where n 1 is number of turns of primary windings L P , n 2 is the number of turns of secondary windings L S , V P is the voltage across primary windings L P , V S is the voltage across secondary windings L S and V 3 is the voltage across both the primary and secondary windings L C .From (1) we get: . P 2 This state starts when all the transistors S 1 , S 2 and S 3 are turned on.All the diodes D 1 , D 2 and D 3 are off in this state.Fig. 3(a) shows the circuit diagram of the proposed converter in this state.Inductors L 1 , L 2 and L P are charged by the supply voltage and the voltages V L1 across L 1 , V L2 across L 2 and V P across L P are positive.Therefore, the currents I 1 through L 1 , current I 2 through L 2 and current I 3 through L P increase linearly with slopes of V S /L 1 , V S /L 2 and V S /L P respectively.Capacitors C 1 and C 2 are disconnected and they neither charge nor discharges.The current I C1 through C 1 and current I C2 through C 2 is zero.Therefore the voltage V C1 across C 1 and voltage V C2 across C 2 are constant.Capacitor C 0 discharges to load, the current I C0 through it is negative and output voltage V 0 decreases linearly with a slope of (-V 0 )/(R 0 C 0 ).This state ends when switch S 3 is turned off at time t=t 1 .

State II
During this state switches S 1 and S 2 are on and switch S 3 is off.Therefore, diodes D 1 and D 2 are off and diode D 3 is on.Fig. 3(b) shows the circuit diagram of the proposed converter in this state.Inductors L 1 and L 2 are still charged by the supply and currents I 1 and I 2 increase with same slopes.Inductor L P discharges through its secondary coupled winding to extension capacitor C 2 .Hence, the current I 3 falls linearly with a slope of {(V S − V C2 )(n 1 /n 1 + n 2 )}/L P .The capacitor C 2 is charged up and voltage V C2 across it increases with a slope of I 3 /C 2 .Capacitor C 1 is still disconnected and V C1 remains constant.Capacitor C 0 still discharges to load and output voltage further falls with the same slope.This state ends when switch S 3 is again turned on at t = t 2 .

State III
This state is similar to State I.All the transistors are on and all diodes are off and the circuit diagram is same as shown in Fig. 3(a).This state starts at t = t 2 and ends at t = t 3 .

State IV
In this state switches S 1 and S 3 are on and switch S 2 is off.The diodes D 1 and D 3 are off and diode D 2 is conducting.The circuit diagram of proposed converter in this state is shown in Fig. 3(c).Inductors L 1 and L P are charged by the supply and current I 1 and I 3 increases with slopes of V S /L 1 and V S /L P respectively.Inductor L 2 and capacitor C 2 discharge to capacitor C 1 and C 1 is charged up.The output capacitor C 0 is still supplying the load and discharges.Current I 2 falls linearly with a slope of V S +V C2 −V C1 )/L 2 and voltage V C2 falls with a slope of (-I 2 )/C 2 .Since C 1 is charged up, voltage V C1 increases with a slope of I 2 /C 1 and output voltage falls with the same slope of (-V 0 )/(R 0 C 0 ).This state ends at t = t 4 when S 2 is again turned on.

State
This state is also similar to State I and State III and it ends at t = t 5 .

State VI (t 5 ≤ t ≤ t 6 )
This state starts when S 1 is turned off at t = t 5 .S 2 and S 3 remain off in this state.Diode D 1 is conducting and diodes D 2 and D 3 are off.Fig. 3(d) shows the circuit diagram of proposed converter in this state.During this state L 2 and L P are charged and I 2 and I 3 rise with slopes of V S /L 2 and V S /L P respectively.C 2 is disconnected and V C2 is constant.L 1 and C 1 are discharged to the load and C 0 is charged in this state.I 1 falls with a slope of (V S +V C1 −V 0 )/L 1 and V C1 falls with a slope of (-I 1 )/C 1 .Output voltage V 0 rises in this state with a slope of I 1 /C 0 − V 0 /(R 0 C 0 ).This state ends when S 1 is turned on again at t = t 6 .

STEADY STATE ANALYSIS OF THE PROPOSED CONVERTER
For the steady state analysis of the proposed converter, the time of each state is expressed in terms of duty cycle D and switching period T S (in seconds) as below: t 0 = 0, t 1 = (DT S −2T S /3), t 2 = T S /3, t 3 = (DT S −T S /3), t 4 = 2T S /3, t 5 = DT S , t 6 = T S .

DC Conversion Ratio
To obtain the dc voltage conversion ratio of the proposed converter, we will use the inductor volt second balance principle on the filtering inductors L 1 , L 2 and L P .Now by the volt second balance of L P we get: .0 Eq. ( 3) can be solved for: . 1 1 Similarly, by the volt second balance of L 2 we get: Solution of Eq. ( 5) gives: .
From Eq. ( 4) and Eq. ( 5) we get: . 2 1 And the volt second balance of L 1 gives: .0 ) )( ( Eq. ( 8) can be solved for: . 1 From Eq. ( 7) and Eq. ( 8) we get: . 3 1 Eq. ( 10) gives the expression for the output voltage of the proposed converter.The dc conversion ratio/voltage gain M is given by: .3 1 Let the ratio of secondary winding of coupled inductor to its primary winding be expressed by x, that is, (n 2 /n 1 ) = x, then the expression of voltage gain can be written as: Technical Gazette 25, 1(2018), 52-59 ).
Since the analysis is done for a three phase version of the proposed converter, number 3 appears in the expression of output voltage and voltage gain.For m number of phases of the proposed converter, the expressions of output voltage and voltage gain are:
Thus by increasing the number of phases m and increasing the ratio x, a higher voltage gain can be achieved.

Voltage Stress of Transistors
The voltage stress of switch S 1 can be found when it is off in State IV.Using Fig. 3(d), the voltage stress V S1 of S 1 is given by: .
Similarly, using Fig. 3(c), the voltage stress V S2 of switch S 2 is given by: .
And using Fig. 3(b), the voltage stress V S3 of switch S 3 can be obtained as: .

SIMULATION RESULTS
To verify the performance of the proposed converter, theoretical and simulation results are obtained for the proposed converter as well as a traditional three phase interleaved boost converter [18] using the parameters listed in Tab. 1.
Fig. 4 shows the simulation results of the proposed for a duty cycle of 70.%.As it is clear from Fig. 4(a), the proposed converter generates an output voltage of 343 volts for 20 volt input.Fig. 4(b) and (c) shows that capacitor C 1 voltage V C1 is 269 volts and voltage across C 2 is 209 volts.Fig. 4(d), (e) and (f) shows the waveforms of voltage stress across Mosfets S 1 , S 2 and S 3 which are all nearly 70 volts.The simulation results show that the proposed converter generates and outputs voltage of 340 volts from a 20 volts input at a duty cycle of 70.%, whereas the traditional 3 phases interleaved boost converter produces the same output at a duty cycle of 94.% which is very high and will cause severe reverse recovery problem.At 70.% duty cycle the traditional interleaved boost converter gives only 73 volts output, thus the voltage gain of the proposed converter is almost five times higher than the traditional interleaved boost converter.Moreover, the voltage stress across the main switches of the proposed converter is only 70 V which is very low, whereas that of the MOSFETs of traditional interleaved boost converter is 340 V. Thus the switching losses in the proposed converter will be less and also low rating MOSFETs can be used which will help in reducing the overall size and cost

EXPERIMENTAL VALIDATION
Experiment is carried out on a two phase version of the proposed converter on a 32 W prototype.The photograph of experimental setup is shown in Fig. 6.For experiment the parameters listed in table II are used.The parameters used for experiment differ from those of simulation due to the lack of some Lab instruments.
Using these parameters in Eq. ( 13) and Eq. ( 14), D=0.6 60 % and M=8.The voltage stress on MOSFETs is 2.5V S for the two phase version of the proposed converter.

CONCLUSION
By using the coupled inductors and voltage extension capacitors a high voltage gain is achieved by the proposed converter.The voltage stress across the main transistor switches which is always equal to the output voltage in traditional interleaved boost converter is considerably reduced.From theoretical analysis, simulation and experimental results it is clear that the two phase version of the proposed converter has three times higher conversion ratio and three times lesser voltage stress across its transistors switches as compared to a traditional two phase interleaved boost converter and the three phase version of the proposed converter has five times higher conversion ratio and five times lesser voltage stress of transistors as compared to a traditional three phase interleaved boost converter.For more than three phases of the proposed converter, the conversion ratio can be higher and voltage stress can be further reduced.These features make the proposed converter a candidate topology for renewable energy applications especially photovoltaic where high step-up dc-dc voltage conversion is essential. .The proposed topology is designed and tested for power ratings of 32 watts.To move the proposed converter topology from laboratory prototypes to industrial applications, the proposed can be tested at high power ratings, that is, at kilo watt level.Further future research on the proposed topology includes developing small signal dynamic model for the proposed converter to realize the closed loop, studying the effects of the proposed converter on the dynamic stability of the dc grids and implementing the proposed converter on higher power and voltage ratings using insulated gate bipolar transistors (IGBTs) instead of Mosfets.

• L 1 =
L 2 = L P = L (where, L is the filtering inductance/phase) • The converter operates in continuous conduction mode (CCM) • Duty ratio D is greater than 66 %.

Figure 1
Circuit diagram of the proposed converter: (a) two phase version of the proposed converter; (b) three phase version of the proposed converter; (c) m phase version of the proposed converter

Figure 2
Steady state waveforms of the proposed converter Technical Gazette 25, 1(2018), 52-59Three PWM signals phase shifted 120 degrees from each other are applied to the gates of the switches S 1 , S 2 and S 3 .The duty ratio All the three PWM signals have the same switching frequency F S , switching period T S and same duty ratio.There are six switching states/modes in one complete switching.Fig.2shows the principle waveforms of the proposed converter and Fig.3gives the circuit diagram of the proposed converter in each state.

Figure 3
Circuit diagram of proposed converter in each state: (a) State I, III and V; (b) State II; (c) State IV, (d) State VI 2.1 State I

Fig. 5
Fig. 5 shows the simulation waveforms of a traditional three phase interleaved boost converter.For 70.% duty cycle the waveform of output voltage is shown in Fig. 5(a) which is only 73 volts.This converter produces an output voltage of 340 volts from 20 volts input at 94.1.%duty cycle as shown in Fig. 5(b).Fig. 5(c), (d) and (e) shows the voltage stress across MOSFETs of traditional 3 phases interleaved boost converter which are all equal to 340 volts.

Figure 4
Figure 4 Simulation waveforms of the proposed converter at 70 % duty cycle: (a) Waveform of output voltage; (b) Waveform of voltage across capacitor C1; (c) Waveform of voltage across capacitor C2 (d) Voltage stress of MOSFET S1; (e) Voltage stress of MOSFET S2; (f) Voltage stress of MOSFET S3

Figure 5
Figure 5 Simulation results of traditional 3 phases interleaved boost converter: (a) Waveform of output voltage at 70 % duty cycle; (b) Waveform of output voltage at 94,1 % duty cycle; (c) Voltage stress of MOSFET S2; (d) Voltage stress of MOSFET S3; (e) Voltage stress of MOSFET S1.

Fig. 7
shows the experimental waveforms.The waveforms of input voltage of 20 volts and the two gate pulses with 60% on time are shown in Fig. 7(a).Fig. 7(b) shows the output voltage and voltage stress across MOSFETs S 1 and S 2 .The output voltage is 150 volts which is close to ideal value of 160 volts.The voltage stress across both the switches S 1 and S 2 is 50 volts which is 2.5 times of the supply voltage.

Figure 6
Figure 6 32 W Prototype of the proposed converter along with experimental setup

Figure 7
Experimental results of the proposed converter at 60 % duty cycle: (a) input voltage and gate pulses; (b) output voltage and voltage stress across MOSFETs S1 and S2

Table 1
Parameters used for simulation

Table 2
Parameters used for experiment