A Flexible Rung Ladder Structured Multilevel Inverter

The tenet of the multilevel inverter (MLI) is a peculiar kind in the voltage source inverter (VSI) family, which offers a prudent solution to prevailing issues of conventional two levels VSI, higher dv/dt and harmonic distortion, through a staircase/stepped output voltage from multiple separate dc sources (SDCs). The incessant research effort in the last four decades has bestowed a host of MLI topologies with different concepts, structures, component requirements and application appropriateness. The main issue with the MLI structures is the objectionable component count while upping the number of levels in the output staircase waveform. This paper suggests a new MLI structure, a flexible rung ladder structured multilevel inverter (FRLSMLI), with a savvy to operate both in symmetrical and asymmetrical modes involving only fewer component counts. The proposed FRLSMLI is basically a ladder structured bridge (H-bridge with additional rungs) and the rungs comprise either source inclusion-bypass cell (SIBC) or four level creator cell (FLCC). The FRLSMLI can synthesize fifteen levels with three SDCs. The simulation and experimental results are projected to validate the viability of proposed MLI in real time applications.


INTRODUCTION
The multilevel inverter (MLI) is a breed of voltage source inverter (VSI), which can synthesize a high quality ac output voltage of required frequency from multiple separate dc sources (SDCs) [1][2][3]. The MLIs strikingly outperform the conventional two level inverters (TLIs) with the apparent merits such as lower dv/dt and device stress, a waned output distortion, minimal switching losses, a gagged electro-magnetic interference (EMI), a low common mode voltage and an ability to operate at higher voltage [4][5][6]. Since its supersession in 1975, many topologies have been readied, which are bizarre in topology, tenet, number of components etc. [7][8][9]. In the wake of above facts, the MLI has become an amenable solution to prevailing issues of the two level inverter [10][11], through which the integration of SDCs like batteries, super capacitors and solar panels has become doable. The evolution of the MLI family started when its first pristine structure, series connection/addition of H-bridges, was introduced by R. H. Baker [12]. As a sequel, in 1980, Nabae A et.al. introduced neutral point clamped (NPC) inverter, which is five level version of the diode clamped MLI [13]. The diode clamped MLI structure employs a specified number ((m−1)/2, where, m is the number of levels) of capacitors to split the single dc voltage source, while the clamping is eventually triumphed by the diodes. This topology curtails the voltage across individual devices with the help of diodes. The successor, capacitor clamped MLI (which is also called flying capacitor), replaced the diodes by floating capacitors [14]. After thirteen years, Gui-Jia Su has suggested an innovative idea of engraving the stair case ac output in dual stage, namely, a first stage to synthesize multilevel dc (a pulsating dc which could result if MLI output is fed to a diode rectifier) and a second stage to fold into ac (conventional H-bridge inverter). Gui-Jia Su has exploited all the three earlier MLI structures and designed three structures of multilevel dc link MLI, respectively [7]. Hitherto, many such proposals have been reported in this ambit [15][16][17][18].
A modified cascaded MLI topology to produce a high number of output steps with fewer switches has been indicated [19]. Additionally, formulaic steps to compute the SDC values have been suggested. A switch sharing strategy has been the crux tenet in the suggestion given by Hew Wooi Ping et al. [20]. It has been demonstrated successfully that a considerable reduction in switch count is possible in the switch sharing. In a dual boost MLI structure, which is a perfect juxtaposition of the L-Z source inverter and the switched capacitor MLI, the first stage of boosting is performed by an impedance network and the second stage is through switched capacitor [21]. J.Venkataramanaiaha et al. have categorized the MLI structures into four clusters, viz. symmetric, asymmetric, hybrid and single dc source topologies [22]. The main drawback of two stage switched capacitor based MLI, higher stress in the second stage devices, has been resolved in the single stage switched capacitor module (S3CM) topology [23]. The S3CM structure asserts the peak inverse voltage (PIV) across all the switches lesser than dc source value.
A topology for reduction of both switching losses and voltage stress has been coined [24], with a voltage balancing tactic. The suggested symmetrical sub-module based MLI, the hybrid cascaded MLI, is the amalgamation of 'n' sub-modules and the H-bridge [25]. A comprehensive comparative study revealed that this topology demands lesser number of components.
Regrettably, even the MLI has few issues. The first one is the requirement of higher number of component count, in particular, more numbers of power semiconductor switches. Despite the fact that the individual switch rating is lesser than in the case of TLIs, the increase in the count also increases the associated gate drivers. Another noticeable issue is number of active devices in the conduction path, which can deduce both the output voltage and increase the conduction losses. This paper develops a MLI structure with dual mode capability (both symmetrical and asymmetrical modes), which paves the solution to the above mentioned problems. The suggested flexible rung ladder structured multilevel inverter (FRLSMLI) is the extended H-bridge structure, wherein special kind of cells are connected in place of the load and hence forms the ladder shape. The rung can include either source inclusion and bypass cell (SIBC) or four level creator cell (FLCC). A rigorous MATLAB R2017b based simulation study is performed for both symmetrical and asymmetrical modes. The result of simulation study is validated in the laboratory prototype supported by field programmable gate array (FPGA) processor.

PROPOSED TOPOLOGY
The generalized structure of the proposed topology pictured in Fig. 1 comprises voltage modules/cells, SIBC and FLCC, which are arranged in rungs of the ladder structure. The ladder structure is resulted while extending the conventional H-bridge with supplementary rungs. The inventive cells are placed in positions of the load that is between two vertical arms. The FLCC contains two SDCs (V1 and V 2 ), which can create four different dc levels (V 1 , V 2 , (V 1 + V 2 ) and (V 1 ∼ V 2 )). S 1 and S 2 are cascading switches while S 1 ' and S 2 ' are bypassing switches. S r is the reverse connector switch, which is responsible for the last level (V 1 ∼ V 2 ) and hence acts as a subtraction facilitator. That is, the S r is a bidirectional switch used to subtract the voltage source (V 2 ) from (V 1 ). The SIBC is a simple cell having one source, where S 3 is the cascading switch and S 3 ' is the bypassing switch. Required number of these cells can be subsumed to attain desired number of voltage levels (m). Fig. 2 to Fig. 8 illustrate the operating modes to extract various levels of the output voltage. For the sake of easy understanding, the asymmetrical combination of SDCs values may be considered as V 1 :V 2 :V 3 = 1:3:3 =1 00 V:300 V:300 V. Fig. 2 depicts the path for obtaining 100 V. Similarly Fig. 3 shows the switching combination for 200 V, which is actually feasible by two ways, either ±(V 2 −V 1 ) or ±(V 3 −V 1 ). The mode diagrams and the different options in achieving certain level are understood by referring to respective figures. Thus with the three SDCs 15 level output is obtained. The clue to the required number of SIBC and FLCC will be more useful. A topology with l number of FLCC will offer a number of voltage levels (m) as (3 × ((4 × l) − 1); a topology with k number of SIBC can offer ((4 × k) − 1) output levels; and a topology with both 'l' number of FLCC and k number of SIBC will give (6 × ((2 × l) + k) − 3) levels. The representative asymmetrical topology, with l = 1 and k = 1, discussed above can offer (6 × ((2 × 1) + 1) − 3) = (6 × (2 + 1) − 3) = (6 × 3 − 3) = 15 levels. Fig. 9 shows a single rung ladder MLI (SRLMLI), which is constituted using either of SIBC and FLCC or both. Using this SRLMLI any number of levels in the output voltage can be obtained. The SRLMLI can be treated as a basic cell to formulate higher levels. A structure involving 0 z number of SRLMLI can generate, m = ((2 (z + 1) -1) if FLCC alone is used while m = (9 × z) if SIBC is used, where respective switch count will be (6 × z) and (9 × z).      Standing voltages on all switches in the supplementary inverter 3 × V dc (5 × V dc ) for z = 1 (7 × 8 (z − 1))V dc (6 × V dc ) for z > 1 Geometric sequence with common ratio 3 Peak output voltage V dc × (2 × z) V dc × ((4 × z) -1) V dc × (((9 × z) − 1)/2) Number of voltage levels ((4 × z) + 1) ((8 × z) -1) (9 × z) Number of SDCs and capacitors (2 × z) (2 × z) (2 × z) Number of switches and gate drivers (9 × z) (9 × z) (9 × z) Standing voltages on all switches in the supplementary inverter 2 × V dc (3 × V dc ) for z = 1 (4 × 9(z − 1))V dc (4 × V dc ) for z > 1

SIMULATION AND EXPERIMENTAL INVESTIGATIONS
For understanding the functioning of the suggested MLI in symmetric and asymmetric modes, a detailed simulation study is carried out in MATLAB R2017b. The simulation parameters are as follows, V 1 = V 2 = 150 V for symmetrical (2 − k); V 1 = 43 V, V 2 = 86 V, V 3 = 172 V (for 1:2:4 ratio) and V 1 = 23V, V 2 = 69 V, V 3 = 207 V (for 1:3:9 ratio) for asymmetrical modes with binary and ternary schemes respectively, to produce 300 V (peak) in the output voltage. Values of the RL load used in simulation study is R = 100 Ω and L = 100 mH. The switching frequency is 2 kHz [27][28][29]. Fig. 10, Fig. 11 and Fig. 12 depict output voltage waveform for symmetric and asymmetric configurations of the proposed topology. Fig.  13 and Fig. 14 charter output voltage spectra and inductive load current waveform for asymmetrical configuration. The simulation results evidence that the proposed topology is capable of giving high number of voltage levels with a minimum number of power components [30][31][32].
The proposed topology is experimentally tested for both symmetrical and asymmetric operations with an identical simulation specification. The experimental setup makes use of Xilinx Spartan 3E FG 320 FPGA controller for generating gating pulses to trigger the switches to synthesize five levels in the output voltage. Fig. 15 and Fig.  16 represent the output voltage waveform for symmetric and asymmetric conditions. Fig. 17 illustrates the inductive load current waveform for the asymmetrical configuration. It is evident from Fig. 15 and Fig. 16 that the proposed topology works well for both operating conditions/ configurations.

CONCLUSION
A new topology in the cascaded breed of the multilevel inverter (MLI) is developed with a view to offer a reduced number of devices in the conduction path while increasing the number of voltage levels. Authors could successfully explore the control degree of freedom available in the MLI structure and suggest an extended H-bridge based cascaded type MLI. The proposed topology has the flexibility of having different voltage ratios and positioning of voltage source modules to offer more voltage levels with a waned count of power switches. The FRLSMLI has been studied well theoretically with mode diagrams and switching tables first, then simulated for symmetrical and asymmetrical modes in MATLAB R2017b. Finally, tested on the designed a laboratory prototype. The study brings a suggestion to use the FRLSMLI for non-conventional energy applications, particularly solar applications. Further, analysis in induction motor drive [33], fault determination [34], transient process [35] etc. can be subsumed for future study.