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Izvorni znanstveni članak
https://doi.org/10.17559/TV-20200826040830
Improvement Energy Efficiency for a Hybrid Multibank Memory in Energy Critical Applications
Jungseok Cho
; Electrical & Electronic Engineering, Sunchon National University, Suncheon, Jeollanam-do, South Korea
Jonghee M. Youn
; Computer Engineering, Yeungnam University, Gyeongsan, Gyeongbuk, South Korea
Doosan Cho*
; Electrical & Electronic Engineering, Sunchon National University, Suncheon, Jeollanam-do, South Korea
| Puni tekst: engleski, pdf (2 MB) | str. 1946-1955 | citiraj | |
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APA 6th Edition Cho, J., Youn, J.M. i Cho*, D. (2020). Improvement Energy Efficiency for a Hybrid Multibank Memory in Energy Critical Applications. Tehnički vjesnik, 27 (6), 1946-1955. https://doi.org/10.17559/TV-20200826040830 MLA 8th Edition Cho, Jungseok, et al. "Improvement Energy Efficiency for a Hybrid Multibank Memory in Energy Critical Applications." Tehnički vjesnik, vol. 27, br. 6, 2020, str. 1946-1955. https://doi.org/10.17559/TV-20200826040830. Citirano 23.01.2021. Chicago 17th Edition Cho, Jungseok, Jonghee M. Youn i Doosan Cho*. "Improvement Energy Efficiency for a Hybrid Multibank Memory in Energy Critical Applications." Tehnički vjesnik 27, br. 6 (2020): 1946-1955. https://doi.org/10.17559/TV-20200826040830 Harvard Cho, J., Youn, J.M., i Cho*, D. (2020). 'Improvement Energy Efficiency for a Hybrid Multibank Memory in Energy Critical Applications', Tehnički vjesnik, 27(6), str. 1946-1955. https://doi.org/10.17559/TV-20200826040830 Vancouver Cho J, Youn JM, Cho* D. Improvement Energy Efficiency for a Hybrid Multibank Memory in Energy Critical Applications. Tehnički vjesnik [Internet]. 2020 [pristupljeno 23.01.2021.];27(6):1946-1955. https://doi.org/10.17559/TV-20200826040830 IEEE J. Cho, J.M. Youn i D. Cho*, "Improvement Energy Efficiency for a Hybrid Multibank Memory in Energy Critical Applications", Tehnički vjesnik, vol.27, br. 6, str. 1946-1955, 2020. [Online]. https://doi.org/10.17559/TV-20200826040830 |
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Sažetak
High performance, low power multiprocessor/multibank memory system requires a compiler that provides efficient data partitioning and mapping procedures. This paper introduced two compiler techniques for the data mapping to multibank memory, since data mapping is still an open problem and needs a better solution. The multibank memory can be consisted of volatile and non-volatile memory components to support ultra-low powered wearable devices. This hybrid memory system including volatile and non-volatile memory components yields higher complexity to map data onto it. To efficiently solve this mapping problem, we formulate it to a simple decision problem. Based on the problem definition, we proposed two efficient algorithms to determine the placement of data to the multibank memory. The proposed techniques consider the characteristic of the non-volatile memory that its write operation consumes more energy than the same operation of a volatile memory even though it provides ultra-low operation power and nearly zero leakage current. The proposed technique solves this negative effect of non-volatile memory by using efficient data placement technique and hybrid memory architecture. In experimental section, the result shows that the proposed techniques improve energy saving up to 59.5% for the hybrid multibank memory architecture.
Ključne riječi
low power; memory system; optimizing compiler; system software; wearable IoT devices
Hrčak ID: 248246
URI
https://hrcak.srce.hr/248246
Moj profil
Srce