Original scientific paper
Digital speed controller implementation for a switched reluctance motor drive using FPGA
Subramanian Vijayan
; Department of Electrical and Electronics Engineering, Anna University, Chenai, INDIA
Shanmugam Paramasivam
; ESAB Engineering Services LTD, INDIA
Rengasamy Arumugam
; Department of Electrical and Electronics Engineering, Anna University, Chenai, INDIA
M. Vasudevan
; Department of Electrical and Electronics Engineering, Anna University, Chenai, INDIA
Shubhransu S. Dash
Abstract
In this paper, a Field-Programmable Gate Array (FPGA) based digital speed control scheme is presented, that is developed to overcome the drawbacks existing in the previous speed control schemes, which were proposed for switched reluctance motor (SRM) drives. It is based on discrete P, PI and PID control algorithm, and requires simple mathematical models. The scheme is implemented by using a XC2S300E FPGA. The real-time experimental results given in this paper show that the speed control method proposed could provide accurate speed control and over a wide range of speeds, and can also perform accurately at different operating conditions (steady state/transient operation under soft chopping mode). The closed loop SRM speed control system is seen to achieve 6.2 RPM speed accuracy, depending on the needed operating speed range, with a step response settling time of 0.25 to 1.05 seconds. Complete descriptions of the experimental system along with FPGA implementation are presented.
Keywords
Switched Reluctance Motor (SRM), speed control, discrete P, PI and PID controller, FPGA
Hrčak ID:
295341
URI
Publication date:
9.12.2006.
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