Izvorni znanstveni članak
https://doi.org/10.1080/00051144.2023.2205725
The design and implementation of folded adaptive lattice filter structures in FPGA for ECG signals
C. Kalamani
; Department of Electronics and Communication Engineering, Dr. Mahalingam College of Engineering and Technology, Pollachi, TN, India
S. Kamatchi
; Department of Electronics and Communication Engineering, Amrita Vishwa Vidhyapeetham, Bangalore, India
S. Sasikala
; Department of Electronics and Communication Engineering, Kongu Engineering College, Perundurai, TN, India
L. Murali
; Department of Electronics and Communication Engineering, P.A. College of Engineering and Technology, Pollachi, TN, India
Sažetak
An adaptive filter is the utmost essential filter castoff in statistical signal dealing. The fine-tuning of the filter factor in relation to the response signal is the adaptive filter's key feature due to fewer calculations, Least Mean Square (LMS) adaptive filters are widely used to remove noise from Electrocardiograms (ECG). The adaptive filters are realized as signal processing algorithms in Digital Signal Processors (DSPs) or in VLSI Signal Processors (VSPs). The technique provides a way to create a folded adaptive lattice LMS filter, which requires less hardware than an adaptive lattice filter. Folding is an algorithm that uses a time scheduling technique that combines arithmetic operations into one operation which reduces Register and silicon chip areas. The design and implementation of a folded lattice adaptive filter remove Power Line Interference (PLI) noise from ECG signals. The MATLAB Xilinx System Generator tool is used to design the Adaptive Lattice LMS Filter and Folded Adaptive Lattice LMS Filter with Folding Order K = 2 and K = 4 and realized in the Virtex 5 FPGA KIT. The results of the folded architecture show that the area is reduced for K = 2 and K = 4 by 82.60% and 91.05%, respectively compared with a normal adaptive lattice filter.
Ključne riječi
Adaptive filter; folding; LMS; SNR; power line interference noise; Virtex5 FPGA
Hrčak ID:
315934
URI
Datum izdavanja:
30.5.2023.
Posjeta: 36 *