Izvorni znanstveni članak

https://doi.org/10.17559/TV-20231122001137

FPGA Implementation of Master-Slave Servo On-Chip Control with Active Disturbance Rejection

Dechun Zheng ; School of Electronic and Information Engineering, Ningbo University of Technology, Ningbo 315016, China
Jiliang Xu ; Ningbo Airport Group Co. LTD, Ningbo 315016, China *
Li Xu ; School of Electronic and Information Engineering, Ningbo University of Technology, Ningbo 315016, China

* Dopisni autor.

Sažetak

In order to improve the anti-disturbance ability of the system and the running speed of PID controller, this paper proposes a design method of master-slave servo on-chip control system with active disturbance rejection control. The active disturbance rejection control (ADRC) technology is introduced into the system, and the friction and interference factors in the system are summed up as disturbances, which are equivalent to the estimation problem of disturbances, and the anti-disturbance ability of the system is improved. The current loop vector control algorithm is normalized, and the parallel computing unit composed of multiplier and adder is used to complete the current loop vector control algorithm under the control of the state machine, which not only improves the running speed of the current loop vector controller, but also reduces the requirement of multiplier resources for FPGA. The experimental results show that the PID controller with ADRC can improve the noise suppression ability of the system to a certain extent. The whole system can be integrated in a low-end FPGA system to reduce the cost of the system, and the current loop vector control algorithm can be completed in 2 us.

Ključne riječi

disturbance rejection control; FPGA; on-chip systems; parallel processing units; vector controller

Hrčak ID:

325997

URI

https://hrcak.srce.hr/325997

Datum izdavanja:

31.12.2024.

Posjeta: 8 *