Izvorni znanstveni članak

https://doi.org/10.17559/TV-20241009002045

Advanced Multiplier Architecture Optimization for Accelerated Arithmetic Operations and its Integration in Wireless Sensor Network Applications

Nirmal Kumar R. ; Department of Electronics and Communication Engineering, Bannari Amman Institute of Technology, Erode, Tamil Nadu, India, 638 401 *
Valarmathi R. S. ; Department of Electronics and Communication Engineering, Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology, Chennai, Tamil Nadu, India, 600062
Kalamani M. ; Department of Electronics and Communication Engineering, KPR Institute of Engineering and Technology, Coimbatore, Tamil Nadu, India, 641407

* Dopisni autor.

Sažetak

Wireless sensor networks (WSNs) are becoming more valuable in environmental monitoring and industrial automation. Many WSN applications need high-performance adders and multipliers for efficient computation. Due to power efficiency, latency reduction, and resource use, optimum designs are required. The Optimized Multiplier Architecture for Wireless Sensor Networks (OMA-WSN) proposed in this paper addresses these issues. WSN mathematical procedures and significance are the subject of this study. WSNs with efficient multipliers and adders are crucial. WSNs cannot use current multiplier designs because of their sluggish operation and high power consumption. OMA-WSN combines RTSBA, Booth Multiplier, and Binary Common Sub-Expression Elimination (BCS2E) algorithms for a new viewpoint. This system's architecture implements efficient computation methods that minimize logic levels and propagation delays. The cutting-edge technique improves power consumption, latency, and resource usage for WSN applications. Numerous simulations demonstrate that the OMA-WSN performs better. The performance of the proposed OMA-WSN was found to be enhanced in various aspects. Specifically, the delay was reduced to 7.56 ns in simulation and 6.32 ns in hardware. The area utilization improved to 98.56 sq. micrometres in simulation and 90.23 sq. in hardware. The power consumption was lowered to 9.87 mW in simulation and 7.56 mW in hardware. The speed increased to 160.43 MHz in simulation and 145.67 MHz in hardware. The energy efficiency was enhanced to 0.98 pJ/bit in simulation and 0.87 pJ/bit in hardware. Lastly, the adder cell utilization improved to 47.43% in simulation and 40.67% in hardware.

Ključne riječi

arithmetic operations; multiplier architecture; optimization; power efficiency; wireless sensor networks;

Hrčak ID:

330572

URI

https://hrcak.srce.hr/330572

Datum izdavanja:

1.5.2025.

Posjeta: 398 *