Izvorni znanstveni članak
https://doi.org/10.32985/ijeces.13.9.11
Design of High-Speed Dual Port 8T SRAM Cell with Simultaneous and Parallel READ-WRITE Feature
Shourin Rahman Aura
; Lecturer, Department of Electrical and Electronic Engineering Ahsanullah University of Science and Technology, Dhaka, Bangladesh
S. M. Ishraqul Huq
orcid.org/0000-0002-0810-6999
; Assistant Professor, Department of Electrical and Electronic Engineering Ahsanullah University of Science and Technology, Dhaka, Bangladesh
Satyendra N. Biswas
; Professor, Department of Electrical and Electronic Engineering Ahsanullah University of Science and Technology, Dhaka, Bangladesh
Sažetak
An innovative 8 transistor (8T) static random access memory (SRAM) architecture with a simple and reliable read operation is presented in this study. LTspice software is used to implement the suggested topology in the 16nm predictive technology model (PTM). Investigations into and comparisons with conventional 6T, 8T, 9T, and 10T SRAM cells have been made regarding read and write operations' delay and power consumption as well as power delay product (PDP). The simulation outcomes show that the suggested design offers the fastest read operation and PDP optimization overall. Compared to the current 6T and 9T topologies, the noise margin is also enhanced. Finally, the comparison of the figure of merit (FoM) indicates the best efficiency of the proposed design.
Ključne riječi
SRAM; CMOS; dual port; figure of merit;
Hrčak ID:
286611
URI
Datum izdavanja:
6.12.2022.
Posjeta: 437 *