Skip to the main content

Automatika : journal for control, measurement, electronics, computing and communications, Vol. 64 No. 3, 2023.

Original scientific paper

https://doi.org/10.1080/00051144.2023.2173121

Investigation and validation of PV fed reduced switch asymmetric multilevel inverter using optimization based selective harmonic elimination technique

T. Jayakumar ; Department of Electrical and Electronics Engineering, Nandha Engineering College, Erode, India
G. Ramani ; Department of Electrical and Electronics Engineering, Nandha Engineering College, Erode, India
P. Jamuna ; Department of Electrical and Electronics Engineering, Nandha Engineering College, Erode, India
B. Ramraj ; Department of Electrical and Electronics Engineering, Nandha Engineering College, Erode, India
Gokul Chandrasekaran ; Department of Electrical and Electronics Engineering, Velalar College of Engineering and Technology, Erode, India
C. Maheswari ; Department of Mechatronics Engineering, Kongu Engineering College, Erode, India
Albert Alexander Stonier ; School of Electrical Engineering, Vellore Institute of Technology, Vellore, India
Geno Peter ; CRISD, School of Engineering and Technology, University of Technology Sarawak, Sibu, Malaysia
Vivekananda Ganji ; Department of Electrical and Computer Engineering, Debre Tabor University, Debre Tabor, Ethiopia

Full text: english pdf 5.896 Kb

page 441-452

downloads: 18

cite

Abstract

Pulse width modulation for Selective Harmonics Elimination (SHE) is mostly employed in the reduction of lower order harmonics. The PV system in this research provides input voltage to the reduced switch 31-level inverter, which is based on the Artificial Bee Colony algorithm. With a high gain DC-DC single-ended primary-inductor converter (SEPIC), the PV panel output voltage is kept constant. The Grey wolf optimization algorithm (GWO) approach is used to get the most power out PV scheme. Multi Carrier modulation, a high-frequency modulation technology, is also used in this novel design of the inverter to reduce upper order harmonics. The suggested Artificial Bee Colony (ABC) algorithm, harmonics is compared to a SHE technique based on a genetic algorithm. The hardware findings were confirmed using DSPIC30F2010 controller simulation, and the recommended system was validated using Matlab simulation.

Keywords

Multilevel inverter; SEPIC converter; selective harmonics elimination; MPPT algorithm; GWO algorithm; multi carrier; DSPIC controller

Hrčak ID:

315762

URI

https://hrcak.srce.hr/315762

Publication date:

14.2.2023.

Visits: 46 *