Izvorni znanstveni članak

https://doi.org/10.17559/TV-20231001000978

IoT based Performance Improvement of Single Instruction Multiple Data (SIMD) Processor Array for Wireless Sensor Networks Application

A. Velliangiri ; Department of ECE, K. S. R. College of Engineering Tiruchengode, Tamilnadu, India *
Vinoth Kumar Kalimuthu ; Department of CSE (AI&ML), SSM Institute of Engineering and Technology, Dindigul, Tamil Nadu, India
C. G. Balaji ; Symbiosis Institute of Digital and Telecom Management (SIDTM) Symbiosis International (Deemed University), Lavale, Pune-412115, Maharashtra, India
Mohan Kumar A. ; Department of ECE, Kongunadu College of Engineering and Technology, Thottiyam, Tamil Nadu, India

* Dopisni autor.

Sažetak

The advent of the Internet of Things (IoT) has brought about the need for more sophisticated and low-cost resource devices compared to traditional embedded systems. These IoT devices, which are often deployed in wireless sensor networks, must operate within strict power constraints. To meet these requirements and to harness the potential of IoT, power consumption planning strategies have evolved, necessitating the integration of new capabilities, including machine learning. In this research, the focus is on migrating machine learning applications onto Field Programmable Gate Arrays (FPGAs) for IoT edge devices, specifically targeting wireless sensor network applications. FPGAs offer flexibility and parallel processing capabilities, making them well-suited for IoT applications where machine learning is increasingly important. A critical component in this work is the development of a Single Instruction Multiple Data (SIMD) processor array, optimized for FPGA implementation. SIMD architectures allow for parallel processing of data, which is essential for efficient machine learning tasks. The research also includes the design and implementation of a multiplier-accumulator (MAC) unit within the SIMD processor array, and an innovative approach is employed using the Dual Field Vedic multiplier. Notably, the researchers opt for the Vedic multiplier design over traditional Booth's method due to its advantages in terms of reducing latency and hardware complexity. The Vedic multiplier, which draws inspiration from ancient Indian mathematics, offers potential performance gains in this context. The research methodology involves creating a high-performance SIMD processor array using FPGA technology and programming it using the Verilog hardware description language. Through FPGA experimentation and analysis, the researchers gather data on various performance metrics. These include area overhead, time delay details, and power consumption parameters.The primary goal of this research is to demonstrate the advantages of the Vedic multiplier in the context of the SIMD system, highlighting its potential to enhance the efficiency and effectiveness of machine learning applications on FPGA-based IoT edge devices. By comparing the results obtained with the Vedic multiplier to those of conventional dual-field multipliers, the research aims to provide valuable insights into the feasibility and benefits of this approach for wireless sensor networks and other IoT applications.

Ključne riječi

dual field vedic multiplier; field programmable gate array multiplier-accumulator; internet of things; single instruction multiple date

Hrčak ID:

325848

URI

https://hrcak.srce.hr/325848

Datum izdavanja:

31.12.2024.

Posjeta: 11 *