Izvorni znanstveni članak
https://doi.org/10.1080/00051144.2024.2395617
Performance-efficient flexible architecture of m–Crypton cipher for resource-constrained applications
Pulkit Singh
; Department of Electronics and Communication Engineering, SRM Institute of Science and Technology, Kattankulathur, India
S. V. S. Prasad
; Department of Electronics and Communication Engineering, MLR Institute of Technology, Hyderabad, India
Shipra Upadhyay
; Department of Electronics and Communication Engineering, Ramaiah Institute of Technology, Bengaluru, India
*
Rajan Singh
; Department of Electronics and Communication Engineering, MLR Institute of Technology, Hyderabad, India
* Dopisni autor.
Sažetak
Some traditional cryptographic techniques, like the Secure Hash Algorithm (SHA-256 for hashing), Rivest-Shamir-Adleman (RSA/Elliptic Curve for signing) and Advanced Encryption Standard
(AES for encryption), perform well on systems with good hardware memory and processing
capabilities. However, these techniques engage in conflict to keep up with the world of sensor
networks and embedded systems. Lightweight cryptography plays a major role in security constraints, especially in resource-limited devices such as RFID tags, smart cards, sensor nodes and
IoT. This paper proposes a flexible hardware architecture of lightweight m-Crypton block cipher
for high-speed resource-constrained applications. The proposed architecture enables a single
architecture appropriate for the many encryptions’ key sizes. Therefore, the proposed architecture changes the security level in resource-constrained applications by integrating several key
sizes into a single design. Furthermore, this architecture outperformed the conventional block
ciphers in terms of throughput-to-area ratio achieving a 10.37 throughput-to-area ratio better
than other lightweight block ciphers. The proposed design can be used in high bandwidth applications, high-end RFID and IoT smart devices. Hence, the proposed design demonstrates that
increasing the speed of cipher implementation results in more plaintext transformations into
ciphertext. All results have been verified and simulated for several Xilinx design suite families.
Ključne riječi
FPGA; hardware implementation; lightweight cryptography; resource-constrained device; throughput
Hrčak ID:
326338
URI
Datum izdavanja:
8.9.2024.
Posjeta: 0 *