INTRODUCTION
1.
ECG, or electrocardiography, is the most used sensor for the electrical behavior recording of the heart as well as the related abnormalities’ diagnosis [1,2]. Existing ECGs ensure data recording using single-to twelve-lead-based recordings [3]. An ECG signal can serve in several environments: hospitals, ambulatories, home monitoring, and also remote monitoring purposes [1]. Even with the particular importance and attention that the academic and industrial researchers provide to ECG signal processing, cardiovascular diseases are still the main reason behind human death in the world [1,4]. The problem comes back to the insufficient effectiveness and real-time capacity of the diagnosis given by existing ECG monitoring systems. Further, the availability of these devices is mainly limited to hospitals due to power supply needs, while they are needed continuously in other environments such as ambulatories. This imposes the development of more effective, real-time, and low-power devices, ensuring long-term availability of the device. Furthermore, an early and predictive diagnosis is a necessity.
Because of direct dependency in processing quality between all ECG signal processing tasks, the preprocessing is a critical stage. Therefore, more interest has been directed to ECG signal filtering, either algorithms, or embedded architecture development. The ECG signal is very weak in the presence of noise. This occurs because its frequency composition belongs to a very low-frequency range. The corrupting noises vary between baseline wander (BW), electromyogram (EMG), power-line interference (PLI), channel noise, random noise, and electrode motion artifacts [1,5–7]. The ECG signal preprocessing literature involves standard as well as hybrid-based methods. These include digital filters (FIR and IIR) [8,9], empirical mode decomposition method (EMD) [10–13], wavelet-based methods [14–18], and models based on artificial intelligence [19,20].
The continuous development in embedded electronics technology has given powerful devices in terms of parallelism and pipeline-deepening capabilities, serving the increasing demand for efficient computing in different fields. These devices vary between CPUs, GPUs, DSPs, FPGAs, and ASICs, which are the most efficient solutions with no reconfigurability and no programmability [21]. Additionally, there are heterogeneous architectures such as system-on-chip (SoC) FPGAs. Further, soft processor-based intellectual property (IP), like the Intel Nios, overcomes the flexibility issue of hard processors. Furthermore, the field programmable analog array (FPAA) is used for analog circuit development [22]. Based on these devices, several ECG signal filtering methods have been deployed. Given that embedded systems are resource limited and that the ECG-based diagnosis is real-time constrained, low computational complexity algorithms must be considered for implementation. However, existing ECG signal denoising architectures implement high-computation-complexity algorithms. This results in insufficient processing time for real-time denoising and high resource consumption (hardware and power), challenging the integration of other treatments and limiting the availability of the said architectures to hospitals, while ECGs are also needed in other environments like ambulatories.
Jenkal et al. suggested in [23,24] a real-time hardware architecture in the favor of the ADTF algorithm. The architecture works under 3.6 kHz. However, this is a higher frequency compared to the required processing of the ADTF. Some years later, Mejhoudi et al. introduced a software system on the basis of multi-core CPUs for the ADTF too [25]. The implementation was performed in the Raspberry Pi 3B+, the Odroid XU4, and a desktop PC with an i5-4200M Core. Thanks to the multiple cores, the preprocessing is ensured in a short time. However, this is performed in a segment-by-segment manner and not sample-by-sample. This means that the data needs to be initially stored, which affects the real-time capacity of the system. Further, such architectures use higher frequencies (gigahertz) and consume more power (watts) because of the unused hardware. Last year, we introduced in [26] an optimized real-time ADTF-based hardware architecture. In that work we dealt with the challenges and limitations in performance and efficiency of the existing embedded system, including anterior architectures of the ADTF. The effectiveness of our architecture was competitive, and it was so efficient and performant.
In [27], an FPGA-based hardware accelerator was proposed for the adaptive max-mean-min algorithm (AMaMeMi) for cleaning physiological signals. Chandra et al. introduced in [28] numerous FPGA-based improved architectures for PLI removal using the adaptive LMS filter. In [29] and in [30], FPGA-based and ASIC-based hardware architectures were suggested by Das et al. for EMD and EEMD processes. In 2022, Elbedwehy et al. introduced a hardware solution for computing the single node reservoir system (SNRC) and the mean filter [31]. FIR filters were also considered by Tripathi et al. for an FPGA-based architecture for different noise removal [32]. The WT was presented by Goel et al. for a hardware implementation using an operating frequency of 180.278 MHz, where the db3 and db2 mother wavelets were considered [33]. More recently, Janwadkar et al. introduced an ASIC-based FIR filter in [34]. The common challenges addressed by these embedded systems are the power, hardware, and time consumption, as well as high processing frequencies.
The DWT-ADTF [15,16] is one of the effective algorithms that have been suggested in the ECG denoising literature. The said algorithm involves the discrete wavelet transform (DWT) technique, a time-frequency analysis technique utilized in signal and image processing, and the adaptive dual threshold filter (ADTF), an adaptive algorithm recently developed for ECG denoising [23,24]. The DWT-ADTF takes its particularity from its low computational complexity, which raises its implementability in different embedded system platforms. Consequently, the denoising quality and low computational complexity tradeoff are effectively addressed by the DWT-ADTF method. Therefore, and within the current work, we suggest an embedded architecture implanting the DWT-ADTF algorithm. The said method had known its first embedded system in 2021, where a hardware architecture was presented by Mejhoudi et al. in [35]. However, the high peaks correction part was not considered, while it is important in recuperating the original high peaks required for heart rate computing. Further, a processing frequency of 50 kHz was used, which is larger than the needed clock cycles for DWT and ADTF computing in a hardware-based architecture. This means that the power consumption of the architecture will be increased due to the useless clock cycles.
In the current work we suggest a software-based architecture implementing the DWT-ADTF for the ECG signal filtering. The proposed solution uses the Nios-V soft processor, which is the newest generation of Intel soft processors. In contrast to hard processors, soft processors represent a highly flexible solution thanks to their configurability in FPGAs. This means that only required hardware and frequencies will be used regarding the considered application needs. Therefore, the power consumption of the whole system will be significantly optimized. On the other side, the core of the Nios-V g (general purpose) comes with a five-stage pipeline, which increases the core’s performance. Furthermore, the instruction set architecture (ISA) of the Nios-V g core is extensible, which raises its deepening with additional hardware accelerators. Consequently, the processor performance will be further increased. To well exploit this hardware capacity for an effective and efficient processing of the ECG signal, we designed an appropriate software architecture. This later ensures real-time processing through a sample-by-sample handling of the ECG data at the level of all processing parts. This manner also allows a good exploitation of the Nios pipeline. Additionally, this avoids the need for any permanent storage of data either before or after processing. Thus, a high amount of unnecessary hardware and consequently of power is reduced. Compared to the considered works, the outcomes of the proposed architecture are significant and convincing.
RELATED WORKS
2.
DWT-ADTF algorithm
2.1.
The DWT-ADTF is a preprocessing technique recently introduced for ECG signals [15]. It is the result of combining the ADTF, recently introduced in [23,24], and the DWT, a famous signal processing method. The ADTF development was not only for responding to ECG signal denoising needs but also for embedded system deployment. Therefore, the ADTF has given very promising denoising quality with very low computational complexity. Additionally, the computational complexity of the ADTF depends only on the size of the input data [24], which raises its implementability in embedded architectures.
In light of the ECG signal’s non-stationarity and the variety of the corrupting noises, the denoising quality of the ADTF has known considerable improvement by the integration of the DWT. This hybridization has conserved the implementability in embedded systems of the resulting algorithm by maintaining its low computational complexity property. This is clearly shown inTable 1, which presents the execution time comparison between the DWT-ADTF and other well-known techniques. The comparison proves that the lowest time corresponds to the DWT-ADTF. This has resulted thanks to the low computational complexity of the DWT-ADTF. Therefore, the DWT-ADTF presents a particular solution for embedded systems targeting ECG signal denoising.
| Algorithm | Execution time (s) |
|---|---|
| DWT-ADTF [16,36] | 0.040 |
| DWT-Thresholding [36] | 0.1189 |
| DWT-NLM [36] | 0.9986 |
| DWT-VMD-NLM [36] | 0.5480 |
| EMD-LM [16] | 0.1620 |
| EEMD-LM [16] | 13.87005 |
The ADTF enhancement has been continued, always considering the denoising quality and algorithmic complexity trade-off. Therefore, a very recent version has been introduced in [16]. Competitive results have been achieved, which reflects the importance of the DWT-ADTF as well as the ADTF itself in the ECG signal filtering field. As a consequence, we propose through the current work an embedded system for the DWT-ADTF process presented in [15]. The denoising principle of the DWT-ADTF involves three main stages: two levels of DWT, ADTF application to the reconstructed signal of the DWT, and finally, the high peaks correction of the ADTF signal.
DWT
2.1.1.
The DWT is a convolution product of the input signal with the coefficients of the chosen wavelet. This process results in the decomposition of the signal into a collection of approximations (A[m]) and details (D[m]). Approximations group low-frequency elements of the signal at the considered decomposition level, while high-frequency components are given by details (D[m]). Approximations and details are calculated according to the equations (1) and (2), respectively [7,15]. L(l) is the low-pass filter of the chosen mother wavelet, while H(l) is its high-pass filter. Reconstructing the original signal is feasible using its approximations and details according to the equation (3) [7,15]. For the DWT-ADTF, the DWT is applied to the noised ECG signal for two decomposition levels. Details D1 and D2 are removed since they concentrate a high amount of high-frequency noises. Therefore, the approximation A2 is twice reconstructed.
ADTF
2.1.2.
The ADTF is an adaptive process of the filtering of ECG signals. It consists of a dual thresholding through a shifting window [23,24]. The thresholds computation is based on the minimum, maximum, and mean values of the shifting window [23]. The thresholds are computed according to the equations (4), (5) and (6), where is the noised signal, that is equal to 0.1 is the thresholding coefficient, and S is the size of the window. In the case of the DWT-ADTF algorithm, the ADTF is applied to the DWT output for a sliding window of eleven samples. More details about the ADTF method can be found in [23,24].
High peaks correction
2.1.3.
This part of the DWT-ADTF algorithm aims at the correction of the high peak amplitude in the ECG signal resulting after the ADTF. The correction principle consists of replacing the QRS regions of the ADTF signal with those of the DWT signal. This is achieved through a sliding window of 1800 samples and a thresholding process, where the threshold is 70% of the window’s maximum.
Main related works
2.2.
Thanks to the continuous development in embedded electronic technology, powerful devices have been introduced. Therefore, numerous embedded architectures for ECG signal filtering have been introduced. A hardware architecture in favor of the ADTF process was suggested by Jenkal et al. in [23,24] for real-time filtering. The proposed solution is a structural and pipelined architecture working under 3.6 kHz. This is quite sufficient to fulfill the real-time processing of the ECG signals. However, it is larger than the required processing of the ADTF, so the unused cycles contribute to increasing power consumption.
In 2021, the ADTF has known another embedded system suggestion. It is a multi-core CPU-based software architecture that was introduced by Mejhoudi et al. in [25]. The proposed solution performed many threads on multiple segments of the input ECG data. Thus, the input data needs to be stored initially, and the number of threads is user-chosen. The software application was developed using C/C++ and the parallel programming tool OpenMP. The implementation was performed in the Raspberry Pi 3B+, the Odroid XU4, and a desktop PC with an i5-4200M processor. Such architectures reduce significantly the processing time. However, the suggested architecture handles the ECG signal as segment-by-segment, which affects the real-time capacity since the data needs to be stored before. Additionally, these architectures use gigahertz and come with additional hardware for communication and transmission to serve different applications. However, these may not be used, which leads to unnecessary power consumption. On the other hand, a desktop PC is not an embedded system since it can’t be integrated into a larger mechanical or electrical system. Furthermore, the Raspberry B3+ and Odroid XU4 are single-board microcomputers designed for specific computing tasks within a larger mechanical or electrical system. However, their ISAs lack hardware flexibility, where they are fixed and can’t be extended. This means that the whole system maximum performance is software-driven within the existing hardware.
In [26], we have introduced an optimized nonstructural hardware architecture for the ADTF. The work consisted of a real-time deep pipelined architecture of six stages working under 1.4 kHz. Significant efficiency and performance have been marked for the suggested system compared to other existing architectures that are based on well-known methods such as the FIR/IIR and EMD.
The DWT-ADTF algorithm had its first known embedded system in 2021 [35], where Mejhoudi et al. proposed an FPGA-based hardware architecture. The introduced solution is a structural architecture, denoising the ECG data within only a DWT and an ADTF processing, without correcting higher peaks attenuated by the ADTF. This significantly influences the denoising effectiveness of the architecture. 50 kHz was the frequency used for data processing. The said frequency is sufficient to achieve real-time ECG signal preprocessing. However, it is larger than the required clock cycles for both DWT and ADTF operations under a hardware-based architecture. Therefore, unused clock cycles will increase the system’s power consumption.
In [27], a software-hardware (SW/HW) architecture was proposed for BW removal, where the max-mean-min algorithm (MaMeMi) was considered. The proposed solution suits different physiological signals, including ECG. The MaMeMi filter presents a cutoff frequency of 17 Hz, which may affect informative low-frequency components of the ECG data. To resolve this, the authors suggested an adaptive MaMeMi (AMaMeMi) to reduce the cutoff frequency to the 0-1 Hz range independently of user input. Therefore, one of the filter parameters is value-fixed, and the other is proportionally linked to the input signal amplitude. However, the introduced filter is not fully adaptive, as a manual mode is enabled for the filter parameter evaluation by the user. This may influence the cutoff frequency of the filter and require an expert user to evaluate its parameters. The MaMeMi represented the hardware part of the SW/HW architecture, while the software side concerned the control mode of the filter parameter computing. The accelerator was implemented in a Xilinx Zynq-7000 SoC FPGA.
In [33], Goel et al. address the challenge of removing PLI from ECG signals. The core algorithm was based on the wavelet packet transform (WPT) and utilized a thresholding technique. The wavelet mothers db3 and db2 were used within a two-level decomposition/reconstruction. The Donoho soft thresholding process was adopted. However, standard hard/soft thresholds cause oscillation or constant deviation, distorting the reconstructed signal. The main contribution of the work is a hardware-efficient architecture designed for real-time operation on FPGAs. This architecture was designed to process data sample-by-sample rather than frame-by-frame, which is essential for true real-time processing. However, high operation frequencies are used, which will lead to high power consumption. Further, the architecture assumes stationary noise, while real-world ECG has complex, non-stationary noise. In 2022, Elbedwehy et al. introduced a single-node reservoir computing system (SNRC) and mean-based filter in [31]. The architecture dealt with the PLI and EMG noises within a floating-point data representation of sixteen bits.
Even with the numerous architectures given in the ECG denoising literature, the hardware, power, and time consumption, the processing frequencies, and the denoising quality are still a challenging trade-off.
METHODS AND MATERIALS
3.
Proposed method
3.1.
The suggested solution is a RISC-V-based software architecture developed with the C language. The Nios processor is a soft processor. This means that it does not physically exist, but it is created by configuring the FPGA logic using a dedicated ecosystem. This provides high flexibility in the logic’s use and distribution according to the application needs. Thanks to the RISC-V ISA’s flexibility, modularity, and open-source property, more instructions and custom hardware accelerators can be integrated, extending the pipeline depth of the Nios core. Therefore, the proposed DWT-ADTF software architecture is designed to take advantage of the existing pipeline’s five stages so that maximum performance can be achieved. Additionally, the proposed DWT-ADTF software architecture is designed to make easier the integration of custom hardware accelerators later.
Configured hardware architecture
3.1.1.
The hardware architecture consists of the Nios-V g core and an on-chip RAM memory component. The interconnection is ensured within a set of standard interfaces such as the Avalon MM (Memory Mapped) and the AXI4 (AMBA Advanced Extensible Interface).Fig. 1 gives a macro view of the whole system hardware.
Thanks to the fluid data loading and processing ensured by the proposed software architecture, no permanent data storage is needed. Therefore, fewer memory RAM cells are required for data preparation, while more cells can be added to caches so that the system performance is increased. Consequently, only 69.34 KB of RAM and 4 KB of cache are needed.
Proposed software architecture
3.1.2.
The software architecture is designed to take advantage of the soft-processor flexibility and the five stages of the Nios core pipeline, avoiding any permanent data storage, reducing memory access needs, and ensuring real-time data loading and processing. Therefore, the data is handled sample-by-sample rather than frame-by-frame, which is essential for true real-time processing.
To represent the ECG data, we used 32-bit floating-point representation. The MIT-BIH Arrhythmia database provides ECG recordings sampled at 360 Hz with 11-bit resolution over a ±5 mV range. The analog-to-digital conversion uses a baseline of 1024 ADC units (corresponding to 0 mV) with a gain of 200 ADC units per mV. Therefore, raw samples are converted to mV using the equation (7). This conversion yields signals in the approximate range of ±5 mV, with the baseline centered at 0 mV.
For databases other than MIT-BIH Arrhythmia, the data should be converted according to the used ADC conditions. Concerning the size of each of the three windows used by our system, the first one used for the convolution is 8 samples which, corresponds to the number of the DWT filter coefficients (db4 wavelet). This window size is database independent. In the ADTF step, a window of 11 samples is used. This size is empirically chosen, where lower MSE is achieved regarding other sizes, as reported by the developers of the ADTF and DWT-ADTF algorithms in the references [23] and [15]. For the high peaks correction, the used window is of 1800 samples (5s). This corresponds approximately to six normal heart beats. The time duration of one normal heartbeat is approximately 0.833 s, so for a 360 Hz sampling rate, six heartbeats correspond to 0.833 s * 360 * 6 = 1800 samples. For other databases, this window size can be adapted according to their sampling rates (e.g., for 250 Hz, the window size should be 1250 samples).
The DWT part involves four convolutional computations. Therefore, four memory regions are allocated for data preparation. Eight elements is the size required for each region since the db4 wavelet mother is used. For the next processing of incoming samples, the previous data are one sample shifted so that the new raw sample is integrated. In this way, convolution computing is continuously ensured without any permanent data storage. On the other hand, the down/up sampling operations occur in a switching manner. This means that one of the two occurs in each processing cycle (newly acquired ECG sample). This reduces the required clock cycles since the up-sampling (zero value insertion) will occur when the down-sampling will not.Fig. 2 details the processing principle of the DWT.
The ADTF is based on a windowing process of eleven samples. Therefore, a memory region of eleven elements is allocated for data preparation. Continuous processing is ensured always by shifting the existing data and inserting new samples.Fig. 3 details the processing principle of the ADTF part.
The high-peaks correction part is based on a windowing and thresholding treatment. Therefore, a nine hundred elements-based memory region is allocated to prepare data. No arithmetic is applied to the incoming data. However, the corrected data is a switch between DWT and ADTF data regarding the threshold-based test. To manage corrected data outputting without any overlapping with the threshold-based test, we separated the two. In addition, the threshold-based test is controlled (activated/deactivated) with a delay. In this way, the corrected data is passed serially to the out, while incoming data are welcome, shifting existing ones. In this manner, the next sample for the threshold-based test is put in the appropriate memory cell before the activation of this latter, and the process goes regularly.Fig. 4 details the processing principle of this part.
The proposed software architecture has well exploited the five-stage pipeline of the Nios processor by avoiding the pipeline stalls.Fig. 5,Fig. 6, andFig. 7 show the pipeline diagrams of the main treatment parts of our system. This concerns the shifted data loading, which prepares data for the DWT, ADTF, and the high peaks correction; the convolution applied in the DWT; and the nested branches used mainly in the DWT and the high peaks correction.
Materials and proof of concepts
3.2.
We validated the suggested DWT-ADTF architecture within two verification approaches: denoising quality and architectural performance. The filtering effectiveness of our architecture is qualitatively and quantitatively assessed in reference to the original software version of the DWT-ADTF process using MATLAB, as well as in comparison with some related and recent works. Therefore, a collection of clinical ECG signals of the MIT-BIH Arrhythmia database are used. The used ones are the signal 100, 101, 103, 113, 115, 117, 119, and 122. These signals are contaminated with different noise types, namely white Gaussian (WGN), blue, and pink noises. The WGN intensity across frequencies is regularly distributed. In contrast, blue and pink noise intensities present a non-regular distribution. The use of noise variety evaluates the robustness of our architecture against such noise distributions.
The robustness of the proposed system toward noise variety is quantified based on a set of benchmarks, namely, the percentage root difference (PRD), mean square error (MSE), and the signal-to-noise ratio improvement (SNRimp). These metrics are computed according to the equations (8), (9), and (10), where x is the authentic signal, is the corrupted signal, and y is the corrected signal. The outcomes can be interpreted as effective for lower MSE and PRD and for higher SNRimp. The suggested architecture is deployed in the Cyclone V DE10 SoC FPGA using the Quartus Prime Lite edition. The architectural efficiency and performance of our suggested embedded system are assessed on the basis of the consumed time, hardware, and power as well as the required processing frequency. Further, these benchmarks are given in comparison with other related and recent works.
RESULTS AND DISCUSSION
4.
Denoising effectiveness evaluation
4.1.
As we have mentioned, the proposed DWT-ADTF software architecture is tested using several original ECG signals corrupted with different noise types. In this subsection we prove qualitatively and quantitatively the denoising efficacy of our proposed architecture.
Qualitative results
4.1.1.
The denoising effectiveness of our architecture is qualitatively proved for some ECG signal cases.Fig. 8 displays the signal 115 denoised by our architecture for 5 dB of blue noise. The figure presents the corrected signal in parallel with its corrupted and original versions.
Such an input SNR value reflects intensive noise presence. According toFig. 8, this intensity is well reduced by the proposed architecture. Another denoising case is given inFig. 9, which presents the case of the signal 103 filtering. This case corresponds to 10 dB of WGN, where a significant correlation is remarked between the reference signal and that corrected by our embedded system.
The QRS is the main characteristic in an ECG signal.Fig. 10 focuses the view on the QRS region in the case of the signal 115. It presents the correction of the white, blue, and pink noise for different input SNR, namely 5, 10, 15, and 20 dB. Each plot case joins the original signal, its noised, and its denoised versions.
This gives a clear qualitative evaluation between the corrected and the original versions of the considered ECG signal. Regarding these outcomes, a high quality of noise correction is given by the suggested architecture, which proves its robustness against noise variety.
Quantitative results
4.1.2.
The denoising efficacy of the introduced architecture is quantified by the averaged MSE, PRD, and SNRimp benchmarks for the noise types and ECG signals previously mentioned.Fig. 11 presents the average SNRimp given by the proposed architecture in comparison with the MATLAB DWT-ADTF and other relevant and recent architectures in the WGN case. Similarly,Fig. 12 provides the comparison of the average MSE metric. In the same manner,Fig. 13 shows the comparison results of the average SNRimp in the blue noise case, whileFig. 14 presents the average PRD for the case of pink noise. According to the aforementioned benchmarks’ results, the proposed architecture gives competitive outcomes at the level of SNRimp and PRD.
In particular, the lowest MSE values are those related to our proposed system. Therefore, these results prove the effectiveness of the introduced solution.
Performance and efficiency evaluation
4.2.
The proposed DWT-ADTF architecture is synthesized under the Intel Quartus Prime Lite edition 23.1, a free edition that includes the required tools for architecture synthesis and implementation.Fig. 15 shows the implementation of our architecture in the Intel Cyclone V DE10 Soc FPGA. The register transfer level (RTL) of the proposed software-based architecture is shown inFig. 16.
The performance of the introduced DWT-ADTF architecture is assessed through the demanded hardware, time, and power.Table 2 presents the time consumed by each part of our architecture as well as that consumed by the whole architecture, where 0.41 ms is consumed in total.
InTable 3 we present the resources consumed by the proposed architecture, where a total of 3945 registers, 9% of logical elements, 6% of DSPs, and 69.34 KB of RAM memory are needed by the proposed solution.
The introduced architecture is compared to various recent ECG signal filtering architectures in terms of the used processing frequency, consumed power, and time, as shown inTable 4. Additionally, the SNRimp and SNRout benchmarks are also considered for a complete comparison. We would like to note that the power consumption reported for our proposed system corresponds only to the power dissipated by the Nios core and the interconnected On-Chip memory, while the other FPGA components are not considered. This is because our objective is the optimization of the digital logic of our architecture using FPGAs, not implementing it in an FPGA. Additionally,Table 4 reports different architecture types (software, hardware, and software/hardware). While it is fair to compare the same types of architecture, this comparison aims to highlight the influence of the underlying algorithms on the efficiency of the resulting architectures, even with hardware-based ones.
According to the presented results, our proposed solution provides promising outcomes, achieving an SNRimp and SNRout in dB of 10.74 and 15.45, respectively. These are the higher values compared to the considered works. This is reached in only 0.41 ms of time, with only 0.97 mW of dynamic power, and under a processing frequency of 50 MHz.
| System part | Execution time (ms) |
|---|---|
| DWT | 0.30 |
| ADTF | 0.09 |
| High peaks correction | 0.005 |
| Full system | 0.41 |
| Resources type | Consumption |
|---|---|
| Registers | 3945 |
| Logical elements (%) | 9 |
| DSPs (%) | 6 |
| RAM (KB) | 69.34 |
| | Algorithm | Architecture | Power | Frequency | Ex. Time (ms) | SNRimp (dB) | SNRout (dB) |
|---|---|---|---|---|---|---|---|
| Proposed | DWT-ADTF | software | 0.97 mW (*) | 50 MHz | 0.41 | 10.74 | 15.45 |
| [15][16] | DWT-ADTF | software | - | - | 40 | 9.17 | - |
| [25] | ADTF | software | 5 /15.5 /90 W | 1.4/2.5 GHz | 2.34 /7.5/ 0.34 | - | 12.5 |
| [27] | MaxMeanMin | software /hardware | 0.7/ 12 mW (HW) | 500 Hz/100 MHz | - | 0.78 | 10.15 |
| [29] | EMD | hardware | 41.93 mW | 50 MHz | 0.0662/ 0.703 (1000 data) | - | - |
| [30] | EMD/EEMD | hardware | - | 50 MHz | 0.0253 (1000 data) | - | - |
| [32] | FIR filter | hardware | 140 mW | - | - | - | - |
| [33] | Wavelet Transform | hardware | - | 177.787/ 195.4 MHz | - | - | - |
| [39] | CS-DAE | hardware | 1.65 W | - | - | 10.5 | - |
| [40] | FIR filter | hardware | 89 mW | 50 MHz | - | - | 6.5813 |
The proposed architecture provides real-time ECG signal filtering since 0.41 ms is very short compared to the 2.33 ms, which is the acquisition rate of the signals of MIT-BIH Arrhythmia. On the other side, the low consumption of the proposed system in terms of hardware enables the integration of further ECG processing, such as feature extraction and classification, for a complete diagnosis in a single electronic chip.
Furthermore, the low consumption of our architecture due to low hardware needs and the low processing frequency reduces the need for a regular power supply. Consequently, this raises its long-term availability inside and outside hospitals.
CONCLUSION
5.
This research paper discussed the development of a real-time FPGA-based embedded system for the DWT-ADTF method. By reason of its five-stage pipeline, high flexibility, and the extensibility of its ISA, the Nios-V soft processor was used. Under a processing frequency of 50 MHz, the five stages of the Nios core pipeline were effectively exploited through the proposed C language-based software architecture. The ECG data was loaded and processed within a sample-by-sample and shifting rather than a frame-by-frame approach. Thus, the ECG signal is preprocessed in real-time, and no permanent data storage is needed.
We verified the architecture’s effectiveness, robustness, performance, and efficiency using various noise types and different ECG signals of the MIT-BIH Arrhythmia database. This was quantified using dedicated benchmarks, including the MSE, PRD, SNRimp, hardware, power, and time consumption, as well as the processing frequency, where the results were compared to other related works. The outcomes of the proposed architecture were promising, as it gave competitive SNR improvement and PRD, while its MSE values were the lowest. The architectural metrics proved the low consumption of our proposed system in terms of time, hardware, and power, where its results outperformed existing architectures. Under a processing frequency of 50 MHz, our architecture implemented less hardware, consuming only 0.41 ms of execution time and 0.97 mW of power. This enables the integration of further treatments in the same electronic chip, namely, feature extraction and disease classification, and raises the long-term availability of such service inside and outside hospitals. Consequently, the proposed architecture represents an appropriate denoising solution that can be integrated into ECG monitoring systems.
The achieved execution time is significant and largely sufficient for denoising task accomplishment. However, more processing stages are required for a complete heart state diagnosis. This means that the denoising time needs to be further reduced so that other processing can be added later. Therefore, and thanks to the extensibility of the Nios-V ISA, we look to accelerating the current architecture. The acceleration will concern the DWT part since it is the most time-consuming process of the whole system. Furthermore, the current architecture deals only with high-frequency noise. Therefore, the denoising effectiveness of our architecture will be improved so that low-frequency noise will also be suppressed.