Izvorni znanstveni članak
https://doi.org/10.1080/00051144.2020.1816388
FPGA implementation of hardware architecture with AES encryptor using sub-pipelined S-box techniques for compact applications
C. Arul Murugan
; Department of Electronics and Telecommunication Engineering, Karpagam College of Engineering, Coimbatore, India
P. Karthigaikumar
; Department of Electronics and Communication Engineering, Karpagam College of Engineering, Coimbatore, India
Sridevi Sathya Priya
; Department of Electronics and Communication Engineering, Karunya Institute of Technology and Sciences, Coimbatore, India
Sažetak
Advanced Encryption Standard (AES) is a thriving cryptographic algorithm that can be utilized to guarantee security in electronic information. It remains to uphold to be resistive from most of the attacks. In this work, AES-128 encryption iterative architecture is designed to achieve minimum area and less hardware utilization. Reduced area is attained by introducing a renovated S-box structure into the AES algorithm. Furthermore, hardware utilization is minimized by incorporating the Vedic multiplier in the Mix column transformation of the AES Encryption process. The proposed encryption architecture is of 128-bit size and was executed on the Xilinx Spartan FPGA series, namely, Spartan 3, Virtex-4 and Virtex-5 devices. The optimization result exhibits that the proposed S-box technique has a smaller area than other existing conventional works.
Ključne riječi
AES; S-box; Vedic multiplier; encryption; decryption
Hrčak ID:
258406
URI
Datum izdavanja:
23.9.2020.
Posjeta: 509 *