Original scientific paper

https://doi.org/10.17559/TV-20251015003067

Improved Phase-Locked Loop Technology under Non-Ideal Grid Conditions Including DC Offset

Jingjing Xia ; Xuhai College, China University of Mining and Technology, Xuzhou 221008, China *
Guodong Cheng ; Xuhai College, China University of Mining and Technology, Xuzhou 221008, China

* Corresponding author.

Abstract

To address the limitations of traditional phase-locked loops (PLLs), including low accuracy, slow dynamic response, and structural complexity under non-ideal grid conditions, this paper proposes an enhanced PLL method based on a second-order generalized integrator (SOGI) and a sinusoidal amplitude integrator (SAI). A mathematical model is established in a two-phase rotating coordinate system to mitigate the effects of unbalanced three-phase voltages and DC offset introduced during sampling. The SOGI first eliminates negative-sequence fundamental voltages, and the SAI subsequently suppresses the DC offset components, ensuring accurate phase extraction from the positive-sequence fundamental voltage. Simulations and hardware experiments confirm that the proposed PLL achieves higher accuracy and a faster dynamic response compared to conventional methods.

Keywords

direct current offset components; phase-locked loop; second-order generalized integrator; sinusoidal amplitude integrator; three-phase voltage unbalance

Hrčak ID:

350401

URI

https://hrcak.srce.hr/350401

Publication date:

31.8.2026.

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