Izvorni znanstveni članak
https://doi.org/10.1080/00051144.2019.1674511
Congestion-aware wireless network-on-chip for high-speed communication
M. Devanathan
; School of Electronics and Communication, REVA University, Bangalore, India
V. Ranganathan
; Department of Electronics and Communication Engineering, Vignans University, Guntur, India
P. Sivakumar
; Department of Electronics and Communication Engineering, Karpagam College of Engineering, Coimbatore, India
Sažetak
The design of system-on-chip (SoC) requires the complex integration between a multi-number of cores on a single chip. To establish the effective communication between multiple cores there aremore challenging issues on designing the network-on-chip (NoC) architectures. The proposed system deals with the utilization of on-chip antennas for the wireless communication between the long distance cores to minimize the latency and power. In this proposed work, we have designed high-speed wireless NoC (WiNoC) for on-chip communication. This high-speed WiNoC has been achieved by designing a congestion measure unit, which monitors and measures the congestion in the input data and establishes the effective wireless communication between the output channels and routers. The designed architecture is synthesized and implemented by using Altera Quartus II, where the SoC is designed using Qsys builder. The proposed WiNoC shows better performance parameters like throughput, latency and power than the conventional NoC.
Ključne riječi
Network-on-chip; network routing; integrated circuit design; system-on-chip; wireless NoC
Hrčak ID:
239853
URI
Datum izdavanja:
3.12.2019.
Posjeta: 805 *