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Fast Packet Switches with Shared Buffer Memory

Liljana Gavrilovska ; Faculty of Electrical Engineering, Skopje, Macedonia

Puni tekst: engleski, pdf (3 MB) str. 319-325 preuzimanja: 66* citiraj
APA 6th Edition
Gavrilovska, L. (1994). Fast Packet Switches with Shared Buffer Memory. Journal of computing and information technology, 2 (4), 319-325. Preuzeto s https://hrcak.srce.hr/150448
MLA 8th Edition
Gavrilovska, Liljana. "Fast Packet Switches with Shared Buffer Memory." Journal of computing and information technology, vol. 2, br. 4, 1994, str. 319-325. https://hrcak.srce.hr/150448. Citirano 24.02.2020.
Chicago 17th Edition
Gavrilovska, Liljana. "Fast Packet Switches with Shared Buffer Memory." Journal of computing and information technology 2, br. 4 (1994): 319-325. https://hrcak.srce.hr/150448
Harvard
Gavrilovska, L. (1994). 'Fast Packet Switches with Shared Buffer Memory', Journal of computing and information technology, 2(4), str. 319-325. Preuzeto s: https://hrcak.srce.hr/150448 (Datum pristupa: 24.02.2020.)
Vancouver
Gavrilovska L. Fast Packet Switches with Shared Buffer Memory. Journal of computing and information technology [Internet]. 1994 [pristupljeno 24.02.2020.];2(4):319-325. Dostupno na: https://hrcak.srce.hr/150448
IEEE
L. Gavrilovska, "Fast Packet Switches with Shared Buffer Memory", Journal of computing and information technology, vol.2, br. 4, str. 319-325, 1994. [Online]. Dostupno na: https://hrcak.srce.hr/150448. [Citirano: 24.02.2020.]

Sažetak
Modern networks (such as BISDN, gigabit networks, parallel computer networks, LANs, etc.) introduce fast packet switches as a new concept of a switching node. Fast packet switches which employ shared storage are able to utilize the buffer efficiently. Several analytical techniques to evaluate the performance of shared buffer switches have been proposed. They range from the simple convolution technique which is fast but inaccurate, to the approach proposed by Eckberg and Hou, which is accurate, but computationally slow. This paper proposes a new approach to performance analysis of shared buffer switches, called the reduced variance approximation (RVA). The new method appears to offer accurate results and efficient computation in comparison to other approaches. Implementation of this method provides reduction in the required shared buffer size.

Ključne riječi
ATM switching; shared buffer; performance analysis; reduced variance approximation

Hrčak ID: 150448

URI
https://hrcak.srce.hr/150448

Posjeta: 112 *