Izvorni znanstveni članak
https://doi.org/10.1080/00051144.2019.1570643
Experimental verification of trinary DC source cascaded H-bridge multilevel inverter using unipolar pulse width modulation
G. Irusapparajan
; Department of EEE, Mailam Engineering College, Mailam, India
D. Periyaazhagar
; Bharath University, Chennai, India
N. Prabaharan
; Department of EEE, School of Electrical and Electronics Engineering, SASTRA Deemed University, Thanjavur, India
A. Rini ann Jerin
; Department of Electrical and Electronics Engineering, Sri Shakthi Institute of Engineering and Technology, Coimbatore, India
Sažetak
Multilevel inverters (MLIs) are an imperative solution for high power and high voltage applications. The MLIs can be classified into two categories such as symmetric and asymmetric. The asymmetric type MLIs has large number of output voltage steps with less number of input DC voltage sources and switching devices. In this paper, a single phase asymmetric (trinary sequence DC source) Cascaded H-Bridge MLI has been developed using unipolar PWM control schemes. The topology can produce 27-level output voltage with the help of 12 switches and 3 DC sources. It has been examined with a diverse combination of multicarrier unipolar PWM control. The PWM control includes Phase Disposition (PDPWM), Alternative Opposition Disposition (APODPWM), Carrier overlapping (COPWM), and Variable Frequency (VFPWM). The harmonic content of output voltage for each technique has been observed with different modulation indices. The demonstration of proposed topology for generating 27-level output voltage has been tested through simulation in MATLAB-SIMULINK and verified with laboratory-based experimental setup. From the results, it is evident that the APODPWM offers quality output voltage with relatively low harmonic distortion. Also, it has been observed that COPWM performance is superior since it delivers relatively higher fundamental RMS output voltage.
Ključne riječi
Asymmetric multilevel inverter; single phase trinary DC source; unipolar PWM; cascaded multilevel inverter
Hrčak ID:
239751
URI
Datum izdavanja:
26.2.2019.
Posjeta: 708 *