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https://doi.org/10.2498/cit.1000731

Optimum Gate Ordering of CMOS Logic Gates using Euler Path Approach: Some Insights and Explanations

Kuntal Roy

Puni tekst: engleski, pdf (662 KB) str. 85-92 preuzimanja: 6.276* citiraj
APA 6th Edition
Roy, K. (2007). Optimum Gate Ordering of CMOS Logic Gates using Euler Path Approach: Some Insights and Explanations. Journal of computing and information technology, 15 (1), 85-92. https://doi.org/10.2498/cit.1000731
MLA 8th Edition
Roy, Kuntal. "Optimum Gate Ordering of CMOS Logic Gates using Euler Path Approach: Some Insights and Explanations." Journal of computing and information technology, vol. 15, br. 1, 2007, str. 85-92. https://doi.org/10.2498/cit.1000731. Citirano 01.03.2021.
Chicago 17th Edition
Roy, Kuntal. "Optimum Gate Ordering of CMOS Logic Gates using Euler Path Approach: Some Insights and Explanations." Journal of computing and information technology 15, br. 1 (2007): 85-92. https://doi.org/10.2498/cit.1000731
Harvard
Roy, K. (2007). 'Optimum Gate Ordering of CMOS Logic Gates using Euler Path Approach: Some Insights and Explanations', Journal of computing and information technology, 15(1), str. 85-92. https://doi.org/10.2498/cit.1000731
Vancouver
Roy K. Optimum Gate Ordering of CMOS Logic Gates using Euler Path Approach: Some Insights and Explanations. Journal of computing and information technology [Internet]. 2007 [pristupljeno 01.03.2021.];15(1):85-92. https://doi.org/10.2498/cit.1000731
IEEE
K. Roy, "Optimum Gate Ordering of CMOS Logic Gates using Euler Path Approach: Some Insights and Explanations", Journal of computing and information technology, vol.15, br. 1, str. 85-92, 2007. [Online]. https://doi.org/10.2498/cit.1000731

Sažetak
The paper addresses some insights into the Euler path approach to find out the optimum gate ordering of CMOS logic gates. Minimization of circuit layout area is one of the fundamental considerations in circuit layout synthesis. Euler path approach suggests that finding a common Euler path in both NMOS and PMOS network minimizes the logic gate layout area. In this article, the minimization of layout area has been placed as equivalent to minimization of the total number of odd vertices in NMOS and PMOS networks. It has been logically proved that a MOS network will always have an even number of odd vertices. Moreover, it intuitively explains how to organize the sequence of NMOS network when deriving PMOS network from it, so that the total number of odd vertices is minimized. The algorithm to determine the total number of optimized solutions is also presented in this paper.

Hrčak ID: 44640

URI
https://hrcak.srce.hr/44640

Posjeta: 6.474 *