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https://doi.org/10.2498/cit.2004.01.01

VHDL Design of a Scalable VLSI Sorting Device Based on Pipelined Computation

Enzo Mumolo

Puni tekst: engleski, pdf (620 KB) str. 1-14 preuzimanja: 3.149* citiraj
APA 6th Edition
Mumolo, E. (2004). VHDL Design of a Scalable VLSI Sorting Device Based on Pipelined Computation. Journal of computing and information technology, 12 (1), 1-14. https://doi.org/10.2498/cit.2004.01.01
MLA 8th Edition
Mumolo, Enzo. "VHDL Design of a Scalable VLSI Sorting Device Based on Pipelined Computation." Journal of computing and information technology, vol. 12, br. 1, 2004, str. 1-14. https://doi.org/10.2498/cit.2004.01.01. Citirano 27.02.2021.
Chicago 17th Edition
Mumolo, Enzo. "VHDL Design of a Scalable VLSI Sorting Device Based on Pipelined Computation." Journal of computing and information technology 12, br. 1 (2004): 1-14. https://doi.org/10.2498/cit.2004.01.01
Harvard
Mumolo, E. (2004). 'VHDL Design of a Scalable VLSI Sorting Device Based on Pipelined Computation', Journal of computing and information technology, 12(1), str. 1-14. https://doi.org/10.2498/cit.2004.01.01
Vancouver
Mumolo E. VHDL Design of a Scalable VLSI Sorting Device Based on Pipelined Computation. Journal of computing and information technology [Internet]. 2004 [pristupljeno 27.02.2021.];12(1):1-14. https://doi.org/10.2498/cit.2004.01.01
IEEE
E. Mumolo, "VHDL Design of a Scalable VLSI Sorting Device Based on Pipelined Computation", Journal of computing and information technology, vol.12, br. 1, str. 1-14, 2004. [Online]. https://doi.org/10.2498/cit.2004.01.01

Sažetak
This paper describes the VHDL design of a sorting algorithm, aiming at defining an elementary sorting unit as a building block of VLSI devices which require a huge number of sorting units. As such, care was taken to reach a reasonable low value of the area-time parameter. A sorting VLSI device, in fact, can be built as a cascade of elementary sorting units which process the input stream in a pipeline fashion: as the processing goes on, a wave of sorted numbers propagates towards the output ports. The paper describes the design starting from an initial theoretical analysis of the algorithm's complexity to a VHDL behavioural analysis of the proposed architecture to a structural synthesis of a sorting block based on the Alliance tools to, finally, a silicon synthesis which was worked out again using Alliance. Two points in the proposed design are particularly noteworthy. First, the sorting architecture is suitable for treating a continuous stream of input data rather than a block of data as in many other designs. Secondly, the proposed design reaches a reasonable compromise between area and time, as it yields an A T product which compares favourably with the theoretical lower bound.

Hrčak ID: 44729

URI
https://hrcak.srce.hr/44729

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