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https://doi.org/10.2498/cit.2000.03.05

Modeling and Simulation of a Hard Real-Time Processor

Matjaž Colnarič
Stjepan Groš
Vlado Glavinić

Puni tekst: engleski, pdf (351 KB) str. 221-233 preuzimanja: 383* citiraj
APA 6th Edition
Colnarič, M., Groš, S. i Glavinić, V. (2000). Modeling and Simulation of a Hard Real-Time Processor. Journal of computing and information technology, 8 (3), 221-233. https://doi.org/10.2498/cit.2000.03.05
MLA 8th Edition
Colnarič, Matjaž, et al. "Modeling and Simulation of a Hard Real-Time Processor." Journal of computing and information technology, vol. 8, br. 3, 2000, str. 221-233. https://doi.org/10.2498/cit.2000.03.05. Citirano 10.12.2019.
Chicago 17th Edition
Colnarič, Matjaž, Stjepan Groš i Vlado Glavinić. "Modeling and Simulation of a Hard Real-Time Processor." Journal of computing and information technology 8, br. 3 (2000): 221-233. https://doi.org/10.2498/cit.2000.03.05
Harvard
Colnarič, M., Groš, S., i Glavinić, V. (2000). 'Modeling and Simulation of a Hard Real-Time Processor', Journal of computing and information technology, 8(3), str. 221-233. https://doi.org/10.2498/cit.2000.03.05
Vancouver
Colnarič M, Groš S, Glavinić V. Modeling and Simulation of a Hard Real-Time Processor. Journal of computing and information technology [Internet]. 2000 [pristupljeno 10.12.2019.];8(3):221-233. https://doi.org/10.2498/cit.2000.03.05
IEEE
M. Colnarič, S. Groš i V. Glavinić, "Modeling and Simulation of a Hard Real-Time Processor", Journal of computing and information technology, vol.8, br. 3, str. 221-233, 2000. [Online]. https://doi.org/10.2498/cit.2000.03.05

Sažetak
Hard real-time systems are increasingly used in various areas of human activity justifying their implementation by means of specialized solutions, mostly of a suitable hardware/software combination. A frequently adopted approach to the realization of the hardware part is based on ASIC, usually a “general purpose” processor which operates according to real-time constraints. In this work the modeling of a processor for the hard real-time domain is described. It is structured as a collection of “task processors” being supervised by another one dedicated to the “kernel” functions. Specifically the behavior of the task processors is modeled using VHDL and subsequently simulated and tested. The paper also addresses the modeling process by determining the detailed requirements on the behavior of the task processor. The outcome of this step influenced the modeling process as the tools used were of restricted functionality and processor behavior enforced a particular decomposition. Because of a restricted VHDL subset available, it was necessary to model the task processor on the lowest level of behavioral abstraction. The task processor has been tested against chosen test programs written in an appropriate assembly language being specially developed for this purpose.

Hrčak ID: 44838

URI
https://hrcak.srce.hr/44838

Posjeta: 516 *