Original scientific paper

https://doi.org/10.17559/TV-20240608001761

Ant Colony Optimized Convolution Neural Network-Long Short Term Memory Based Energy Conservation in Variation-Tolerant Near-Threshold Processor

C. Thiruvengadam ; Department of Electronics and Communication Engineering, Anjalai Ammal Mahalingam Engineering College, Thiruvarur 614 403, Tamil Nadu, India
Mashael Maashi ; Department of Software Engineering, College of Computer and Information Sciences, King Saud University, Po box 103786, Riyadh 11543, Saudi Arabia
Jamal Alsamri ; Department of Biomedical Engineering, College of Engineering, Princess Nourah bint Abdulrahman University, Saudi Arabia
Raghu Gundaala ; Department of ECE, Saveetha School of Engineering, Saveetha Institute of Medical and Technical Sciences, Chennai, India *

* Corresponding author.

Abstract

When considering the reduction of profit margins and improvement of energy efficiency in processors operating at near-threshold and sub-threshold levels, exploring timing error resilience might be seen as a potentially profitable option. Near-threshold (NT) circuit design is increasingly used for building energy-efficient digital circuits. One drawback was a drop in performance due to a reduction in driving current. To maximize energy economy and minimize performance deterioration, some studies advocate non-traditional (NT) chip multiprocessors. The creation of energy-efficient artificial intelligence technologies has gained popularity recently. Graphics processing units and general-purpose CPUs could not match the goal of efficiency and performance. A semiconductor with many processing units was created to do this. This goal was achieved by engineering the hardware with unique features. Therefore, this study constructs an ACO_CNN+LSTM (Ant Colony Optimised Convolution Neural Network-Long Short Term Memory) neural network to achieve lower power consumption without compromising performance. In this method, Ant Colony Optimization (ACO) is used to explore and select optimal configurations of CNN and LSTM architectures, minimizing energy usage through efficient layer selection, filter size adjustment, and neuron pruning. By incorporating Dynamic Voltage and Frequency Scaling (DVFS) and operating at near-threshold voltages (NTV) - where the supply voltage is just above the transistor threshold - power consumption is further reduced, as the processor can function at lower voltage levels while tolerating variations in performance. This hybrid ACO-driven optimization enhances both CNN feature extraction and LSTM's temporal processing by selecting the most energy-efficient network parameters. As a result, the proposed ACO_CNN+LSTM achieves 12.73% of energy consumption, 9.46 sec of latency, 98.45% of normalized frequency, 22.64% of error rate and 31.67% of processor utilization.

Keywords

chip processor; convolution neural network; energy conservation; long short term memory; near-threshold; optimization

Hrčak ID:

328636

URI

https://hrcak.srce.hr/328636

Publication date:

27.2.2025.

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