Izvorni znanstveni članak
https://doi.org/10.24138/jcomss.v2i3.288
High throughput implementation of an adaptive serial concatenation turbo decoder
Maurizio Martina
; Department of Electronics, Politecnico di Torino,Italy
Andrea Molino
; Department of Electronics, Politecnico di Torino,Italy
Fabrizio Vacca
; Department of Electronics, Politecnico di Torino,Italy
Guido Masera
; Department of Electronics, Politecnico di Torino,Italy
Guido Montorsi
; Department of Electronics, Politecnico di Torino,Italy
Sažetak
The complete design of a new high throughput adaptive turbo decoder is described. The developed system is programmable in terms of block length, code rate and modulation scheme, which can be dinamically changed from frame to frame, according to varied channel conditions or user requirements. A parallel architecture with 16 concurrent SISOs has been adopted to achieve a decoding throughput as high as 35 Mbit/s with 10 iterations, while error correcting performance are within 1dB from the capacity limit. The whole system, including the iterative decoder itself, de-mapping and de-puncturing units, as well as the input double buffer, has been mapped to a single FPGA device, running at 80 MHz, with a percentage occupation of 54%.
Ključne riječi
turbo codes; channel decoders; parallel architectures; VLSI implementation
Hrčak ID:
180860
URI
Datum izdavanja:
22.9.2006.
Posjeta: 731 *