Izvorni znanstveni članak

https://doi.org/10.17559/TV-20210719025814

Performance Improvement of SIMD Processor for High-Speed end Devices in IoT Operation Based on Reversible Logic with Hybrid Adder Configuration

Vinoth Kumar Kalimuthu* orcid.org/0000-0002-8920-4936 ; Department of Electronics & Communication Engineering, SSM Institute of Engineering and Technology, Dindigul, Tamil Nadu, India-624002
Karthikeyan Somasundaram ; Department of Electronics & Communication Engineering, SSM Institute of Engineering and Technology, Dindigul, Tamil Nadu, India-624002
Bhavani Sridharan ; Department of Electronics & Communication Engineering Sri Sakthi Institute of Engineering and Technology, Coimbatore, Tamil Nadu, India-641062
Vennila Chockalingam ; Department of Electronics & Communication Engineering Saranathan College of Engineeering, Trichirappalli, Tamil Nadu, India-620012

Sažetak

The reversible logic function is gaining significant consideration as a style for the logic design by implementing modern Nano and quantum computing with minimal impact on physical entropy. Recent advances in reversible logic allow for computer design applications using advanced quantum computer algorithms. In the literature, significant contributions have been made towards reversible logic gate structures and arithmetic units. However, there are many attempts to dictate the design of Single Instruction-Multiple Data (SIMD) processors. In this research work, a novel programmable reversible logic gate design is verified and a reversible processor design suggests its implementation of SIMD processor. Then, implementing the ripple-carry, carry-select and Kogge-Stone carry look-ahead adders using reversible logic and the performance is compared. The proposed reversible logic-based architecture has a minimum fan out with binary tree structure and minimum logic depth. The simulation result of the proposed design is obtained from Xilinx 14.5 software. From the simulated result, the computational path net delay for 16 × 16 reversible logic with Kogge Stone Adder is 17.247 ns. Compared with 16-bit Kogge Stone Adder, the reversible logic-based 16-bit Kogge Stone Adder gives low power and low time delay. By looking at the speed, energy and area parameters, including fast applications in which two smaller delay and low power adders are required, the effectiveness, including the proper area use of the hybrid adder recommended by it is evaluated.

Ključne riječi

IoT; Kogge-Stone carry look-ahead; quantum; reversible logic; single instruction-multiple data

Hrčak ID:

269507

URI

https://hrcak.srce.hr/269507

Datum izdavanja:

15.2.2022.

Posjeta: 1.548 *