Izvorni znanstveni članak
https://doi.org/10.32985/ijeces.14.2.11
Design and Implementation of a Simulator for Precise WCET Estimation of Multithreaded Program
P. Padma Priya Dharishini
orcid.org/0000-0003-1059-428X
; Department of Computer Science and Engineering Ramaiah University of Applied Sciences Bangalore, India
P.V.R. Murthy
; Department of Artificial Intelligence and Data Science Nitte Meenakshi Institute of Technology Bangalore, India
Sažetak
Significant attention is paid to static analysis methods for Worst Case Execution Time Analysis of programs. However, major effort has been focused on WCET analysis of sequential programs and only a little work is performed on that of multithreaded programs. Shared computer architectural units such as shared instruction cache pose a special challenge in WCET analysis of multithreaded programs. The principle used to improve the precision of shared instruction cache analysis is to shrink the set of interferences, from competing threads to an instruction in a thread that may be accessed from shared instruction cache, using static analysis extended to barriers. An Algorithm that address barrier synchronization and used by the simulator is designed and benchmark programs consisting of both barrier synchronization and computation task synchronization are presented. Improvements in precision upto 20 % are observed while performing the proposed WCET analysis on benchmark programs.
Ključne riječi
Worst Case Execution Time Analysis; Shared Instruction Cache Analysis; Multithreaded Program; Multicore Architecture;
Hrčak ID:
294591
URI
Datum izdavanja:
27.2.2023.
Posjeta: 293 *