Original scientific paper

https://doi.org/10.17559/TV-20241227002215

Hybrid Logic Locking Using Horned Lizard Optimization and Q-Learning for Secure Hardware Design

Karthik S. ; Department of ECE SRM Madurai College for Engineering and Technology, Sivagangai, Tamil Nadu, India *
Sujatha C. ; Department of CSE SSM Institute of Engineering and Technology, Dindigul. Tamil Nadu, India
Premkumar M. ; Department of ECE SSM Institute of Engineering and Technology, Dindigul.Tamil Nadu, India

* Corresponding author.

Abstract

Logic locking has become an essential technique for safeguarding intellectual property (IP) in hardware designs against reverse engineering and tampering. However, existing methods often rely on the random insertion of key gates in original circuits, neglecting critical factors such as area overhead and output corruption rates. This paper presents a novel hybrid logic locking technique aimed at maximizing security while minimizing the overhead of key gate insertion. The proposed method integrates the Horned Lizard Optimization (HLO), a metaheuristic inspired by the adaptive defense strategies of horned lizards, with a Q-learning model. The Q-learning component enhances the exploration stage of HLO, enabling the optimal selection of insertion points for key gates in the circuit. Experimental evaluations on benchmark circuits demonstrate that the proposed technique achieves an average area, delay, and power overhead of 16.85%, 0.0475%, and 2.3345%, respectively, outperforming state-of-the-art methods in terms of efficiency and security.

Keywords

hardware security; horned lizard optimization; intellectual property protection; logic locking; Q-Learning

Hrčak ID:

335074

URI

https://hrcak.srce.hr/335074

Publication date:

30.8.2025.

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