Izvorni znanstveni članak
https://doi.org/10.1080/00051144.2019.1631568
Artificial neural network model for arrival time computation in gate level circuits
S. R. Ramesh
; Department of Electronics and Communication Engineering, Amrita School of Engineering, Coimbatore, India
R. Jayaparvathy
; Department of Electronics and Communication Engineering, Sri Sivasubramaniya Nadar College of Engineering, Chennai, India
Sažetak
Advances in the VLSI process technology lead to variations in the process parameters. These process variations severely affect the delay computation of a digital circuit. Under such variations, the various delays, i.e. net delay, gate delay, etc., are no longer deterministic. They are random in nature and are assumed to be probabilistic. They keep changing, based on factors such as process, voltage, temperature, and a few others. This calls for efficient tools to perform timing checks on a design. This work presents a technique to compute the arrival time of a digital circuit. The arrival time (AT) is computed using two different timing engines, namely, static timing analysis (STA) and statistical static timing analysis (SSTA). This work also aims to eliminate number of false paths. It uses a fast and efficient filtering method by utilizing ATPG stuck-at faults and path delay faults. ISCAS-89 benchmark circuits are used for implementation. The results obtained using the probabilistic approach are more accurate than the conventional STA. It has been verified with an Artificial Neural Network (ANN) model. The arrival time calculated using SSTA shows 7% improvement over that of STA. The absolute error is reduced twofold in the case of the ANN model for SSTA.
Ključne riječi
Static timing analysis; statistical static timing analysis; arrival time; false paths; artificial neural network
Hrčak ID:
239810
URI
Datum izdavanja:
28.7.2019.
Posjeta: 824 *