Tehnički vjesnik, Vol. 32 No. 5, 2025.
Izvorni znanstveni članak
https://doi.org/10.17559/TV-20250103002231
Performance Enhanced Penta-MTJ Based Logic Gates Using FinFET for Low Power and High-Speed Applications
V. M. Senthilkumar
; Department of Electronics Engineering (VLSI Design and Technology), Rajalakshmi Institute of Technology (Autonomous), Chennai-600 124, Tamil Nadu, India
K. Kalaiselvi
; Department of Networking and communications, Faculty of Engineering and technology, SRM Institute of science and technology, Kattankulathur, Tamil Nadu-603203, India
K. Umadevi
; Department of EEE, Sengunthar Engineering College (Autonomous), Tiruchengode -637 205, Namakkal Dt. Tamil Nadu, India
K. Vinoth Kumar
orcid.org/0000-0002-8920-4936
; Department of CSE (AI&ML), SSM Institute of Engineering and Technology, Dindigul, Tamil Nadu, India
*
* Dopisni autor.
Sažetak
The performance of conventional CMOS circuits can be enhanced using advanced devices and technologies to address the growing gap between device fabrication and computing system design. Spintronic devices, particularly magnetic tunnel junctions (MTJs), have emerged as a promising solution for improving CMOS performance by offering faster execution, lower power consumption, and infinite endurance. MTJs are highly suitable for designing and implementing memory and logic circuits. This paper introduces the implementation of a PentaMTJ-based logic gate using FinFET technology. The proposed design features self-referencing, cascading capability, and operation at reduced voltage levels, effectively eliminating the headroom issue in pre-charge sense amplifiers. The proposed architecture ensures faster reading and writing operations while minimizing power consumption and leakage currents due to the FinFET-based design. To validate the functionality of the MTJ device, a BRAUN multiplier is cascaded with a shift register using MTJ technology. Comparative analysis indicates that MTJ devices offer superior cascading performance, reduced static power dissipation, and lower voltage headroom. The implementation and simulation were conducted using the Synopsys Analog Design Module.
Ključne riječi
FinFET Technology; CMOS performance enhancement; low power design; magnetic tunnel junction (MTJ); penta-MTJ
Hrčak ID:
335076
URI
Datum izdavanja:
30.8.2025.
Posjeta: 756 *