Original scientific paper

https://doi.org/10.17559/TV-20250406002559

Compact and High-Performance QCA-Based Adder Design Using an Optimized XOR Logic Structure

V. Bhuvaneswari ; Department of ECE, SRM Institute of Science and Technology, City Campus, Vadapalani, Chennai,Tamil Nadu, India *
S. Yuvaraj ; Department of ECE, SRM Institute of Science and Technology, SRM Nagar, Kattankulathur, Chennai,Tamil Nadu, India

* Corresponding author.

Abstract

Quantum-dot Cellular Automata (QCA) has emerged as a viable nanotechnology for implementing ultra-dense, low-power digital logic circuits, offering significant advantages over traditional CMOS technology in terms of power consumption and device scalability. This paper presents an efficient design approach for constructing QCA-based half adder and full adder circuits using a novel, highly compact XOR gate configuration. The proposed XOR gate requires only 8 quantum dots, which significantly reduces the overall complexity and area of the arithmetic circuits. The design methodology utilizes the concept of half-cell distance optimization and effective cell-to-cell interaction to achieve reduced latency and minimal crossover usage. The QCADesigner simulation tool is employed to validate the correctness and performance of the proposed circuits. Comparative analysis is carried out against previously reported QCA-based adder designs, considering key performance metrics such as cell count, number of wire-crossings, and propagation delay. The simulation results reveal that the proposed half adder and full adder designs outperform existing counterparts in terms of compactness and operational efficiency. Furthermore, the proposed layouts are fully planar and do not require multilayer crossovers, thereby simplifying fabrication and enhancing practical applicability. The findings demonstrate that the compact XOR gate-based approach provides a scalable and power-efficient solution for implementing fundamental arithmetic operations in future nanoelectronic systems. This work highlights the potential of QCA as a next-generation design paradigm for low-power computing architectures.

Keywords

digital adders; low-power logic design; nano arithmetic circuits; quantum-dot cellular automata (QCA); XOR gate optimization

Hrčak ID:

342635

URI

https://hrcak.srce.hr/342635

Publication date:

31.12.2025.

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