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Engineering Review : International journal for publishing of original researches from the aspect of structural analysis, materials and new technologies in the field of mechanical engineering, shipbuilding, fundamental engineering sciences, computer sciences, electrical engin, Vol. 36 No. 3, 2016.

Original scientific paper

A New DFT Architecture to Reduce Test Data Volume and Test Application Time

Zhang Ling
Kuang Jishun ; School of Computer, Hubei Polytechnic University, Huangshi,
Mei Junjin

Full text: english PDF 879 Kb

page 197-202

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Abstract

This paper proposes a new DFT Architecture that contains three test scan modes. The test data could be interval broadcast to scan chains whenever the data in corresponding locations are compatible. Compared with the conventional broadcast scan architecture, the proposed architecture achieves better compression ratio in all cases, and the test application time is also induced. The hardware overhead is very low. Both theoretical and experimental results prove efficacy and versatility of the proposed scheme.

Keywords

test data compression; integrated circuits; broadcast architecture; design for test

Hrčak ID:

165657

URI

https://hrcak.srce.hr/165657

Publication date:

12.9.2016.

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